Geneseo is the codename for an enhancement to PCI Express. Lead by Intel and IBM, this technology will make it easier for co-processor vendors to produce accelerator cards. Among other improvements, Geneseo includes new semantics that reduce the overhead of signaling and synchronization, which makes more efficient interaction between the application software and the accelerator chip.
Intel’s work on Geneseo appears to take aim at blunting AMD’s work on Torrenza, which allows accelerators to plug into AMD processor sockets and communicate with the CPU via HyperTransport. The concept behind Torrenza is already being used by DRC.
It is important to note that Geneseo and Torrenza represent two completely different means of aiding co-processors. The former is an enhancement to the bus architecture, whereas the latter leverages the direct connect architecture. AMD of course still has the HTX expansion slot, but this has not been as widely used as PCI Express. And Intel still has its work on CSI, which should debut any decade now.