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Intel at HPCC

I’m at the High Performance Computing and Communications conference in Rhode Island this week. It’s a great conference; I’m glad I came and will come again (more here).
Anyway, I’m summarizing some of the high points that I hear from the speakers and panels in articles to be published in this week’s HPCwire. If you couldn’t make the conference, you should definitely check my Cliff’s Notes.

As a teaser, here are some of the nuggets I teased out of Intel’s presentation

Stephen also talked about the roadmap and the two year beat with 45nm appearing this year, 32nm in 2009, 22nm in 2011, and all the way down to 8nm in 2017. The technology model has the first year of a two year couplet shrinking the preceding year’s architecture, and the second year introducing a new microarchitecture. It’s Penryn first, then Nehalem, followed by Westmere and Gesher in the 2009 couplet. God help me, it’s starting to make sense.

Stephen also talked about the research that Intel is doing on the tension between a few complex cores, many simple cores, and a hybrid between the two. In this context he talked about getting performance out of these systems by stacking improvements: adding cores, using hardware thread scheduling, improving cache, and then adapting the instruction set. Along the way Stephen touched on one of Intel’s design targets: deliver all this improvement without breaking the current programming models. A tough challenge.

More details in the article; look for it tomorrow night on the web site or in a mail client near you.

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