Comments on: Another Trip Down Low Latency Lane http://insidehpc.com/2007/09/12/another-trip-down-low-latency-lane/ HPC News Without the Noise for Supercomputing Professionals | insideHPC Sun, 19 May 2013 10:46:54 +0000 hourly 1 http://wordpress.org/?v=3.1.1 By: John Leidel http://insidehpc.com/2007/09/12/another-trip-down-low-latency-lane/#comment-9197 John Leidel Thu, 13 Sep 2007 17:41:04 +0000 http://insidehpc.com/2007/09/12/another-trip-down-low-latency-lane/#comment-9197 I'm not sure if Mellanox can do it at the hardware level or not. I know with MVAPICH MPI, you can certainly bond the two ports. Its especially advantageous to do so in multi-rail fabrics. I’m not sure if Mellanox can do it at the hardware level or not. I know with MVAPICH MPI, you can certainly bond the two ports. Its especially advantageous to do so in multi-rail fabrics.

]]> By: Ron Van Holst http://insidehpc.com/2007/09/12/another-trip-down-low-latency-lane/#comment-9196 Ron Van Holst Thu, 13 Sep 2007 17:35:47 +0000 http://insidehpc.com/2007/09/12/another-trip-down-low-latency-lane/#comment-9196 This look like another form factor for the HCA Mellanox announced in the spring. I wonder what Qlogic/PathScale are doing with their low latency HCA, haven't heard much on that lately. I wonder if Mellanox can load share across the 2 IB ports, or if it's just a sparing scenario. This look like another form factor for the HCA Mellanox announced in the spring. I wonder what Qlogic/PathScale are doing with their low latency HCA, haven’t heard much on that lately.

I wonder if Mellanox can load share across the 2 IB ports, or if it’s just a sparing scenario.

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