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DRC intros Impulse C front end

DRC announced [warning, PDF] last week that they’ve teamed up with Impulse Accelerated Technologies to provide an Impulse C optimizing C-to-FPGA compiler front end to support DRC’s RPU (recall that Cray is using DRC’s RPU in the FPGA part of its recently announced XT5h computer).

The new integration extends the access to this architecture to more fully include software developers. Previously, a software developer would need to understand how to write the lower level (HDL) routines to be able to access the memory and I/O of the RPU. The new integration also creates a powerful methodology of co-design. In this new scheme, developers can write C code, and partition it between the Opteron and the FPGA. In this configuration, the processor can handle single stream, memory intensive processes and the FPGA can handle processes which contain internal pipelines which can be unrolled. Unrolling these loops creates a parallel processing approach which leverages the Xilinx FPGA at the core of the reconfigurable system.

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