Last week IBM’s Zurich research team and its partners were talking about progress on 3D integration as a path for continuing the Moore’s law growth of transistors. The argument is that we won’t be able to stay on the Moore’s law density curve for another 15 years by virtue of diminishing feature size alone — thus the research in new packaging and cooling technologies.
Last week, IBM, École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH) signed a four-year collaborative project called CMOSAIC to understand how the latest chip cooling techniques can support a 3D chip architecture. Unlike current processors, the CMOSAIC project considers a 3D stack-architecture of multiple cores with a interconnect density from 100 to 10,000 connections per millimeter square. Researchers believe that these tiny connections and the use of hair-thin, liquid cooling microchannels measuring only 50 microns in diameter between the active chips are the missing links to achieving high-performance computing with future 3D chip stacks.
“In the United States, data centers already consume two percent of the electricity available with consumption doubling every five years. In theory, at this rate, a supercomputer in the year 2050 will require the entire production of the United States’ energy grid,” said Prof. John R. Thome, professor of heat and mass transfer at EPFL and CMOSAIC project coordinator. 3D chip stacks with interlayer cooling not only yield higher-performance, but more importantly, allow systems with a much higher efficiency, thereby avoiding the situation where supercomputers consume too much energy to be affordable.