Altera Coporation today announced the latest addition to its Stratix family of FPGAs. The Stratix V series leverages the latest TSMC 28-nm High Performanc manufacturing process. In migrating to the new process, Altera has built in a myriad of new features, including 1.6 Tbps of serial switching capability. The new Stratix V’s also have up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18×18 multipliers and integrated transceivers operating up to an industry-leading 28 Gbps.
The innovations we made in our fifth-generation Stratix family dramatically improve the density and I/O performance of our high-end devices, further strengthening the FPGAs’ competitive position versus ASICs and ASSPs,” said Vince Hu, vice president of product and corporate marketing at Altera Corporation. “Altera remains committed to solving the challenge of increasing bandwidth while staying within designer’s cost and power requirements. From the core to the I/O, we touched all aspects of Stratix V FPGAs to ensure they deliver the highest level of performance, density and integration.”
A quick look at the new feature list:
- Stratix V GT FPGA — Industry’s only FPGA with integrated 28-Gbps transceivers targeting 100G systems and beyond.
- Stratix V GX FPGA — Supports a wide range of applications with 600-Mbps to 12.5-Gbps transceivers.
- Stratix V GS FPGA — Optimized for high-performance digital signal processing (DSP) applications with 600-Mbps to 12.5-Gbps transceivers.
- Stratix V E FPGA — Highest density FPGA ideal for ASIC prototyping, emulation or high-performance computing applications.
- New adaptive logic module (ALM) architecture — adds up to 800K additional registers in the largest device to maximize logic efficiency. The ALM architecture is ideal for heavily pipelined and register-rich designs.
- Enhanced embedded memory structure featuring M20K blocks — offers improved area efficiency and higher performance.
- Industry’s first variable-precision DSP block — provides the highest efficiency and performance across multiple-precision DSP data paths.
- User friendly partial reconfiguration — allows designers to reconfigure part of the FPGA while other sections remain running.