Comments on: TACC On Memory Performance in a Cluster http://insidehpc.com/2010/07/29/tacc-on-memory-performance-in-a-cluster/ HPC News Without the Noise for Supercomputing Professionals | insideHPC Sun, 19 May 2013 10:46:54 +0000 hourly 1 http://wordpress.org/?v=3.1.1 By: John Leidel http://insidehpc.com/2010/07/29/tacc-on-memory-performance-in-a-cluster/#comment-242710 John Leidel Fri, 30 Jul 2010 13:33:40 +0000 http://insidehpc.com/?p=12766#comment-242710 Robert L, the answer to your question is not 100% clear, but falling much closer to 'YES'. There are plenty of folks that preach "bandwidth, bandwidth, bandwidth." This is very much true. You're also correct that there doesn't seem to be quantum leaps in memory bandwidth coming down the pipe in the near future. However, as bandwidth continues to creep up, we need to remember the 'other' memory performance factor: latency. The latency required to fetch a single cache line from a DRAM is reasonably high [as compared to cache and registers]. This latency has not improved over time at the same scale that transistor density has [eg, Moore's Law]. The moral of the story is, we need to spend more time focusing on the memory performance of applications and architectures. This story includes two main chapters: memory bandwidth and memory latency [how to cover latency with outstanding operations and reducing the latency with new technologies]. Do a google search on 3D Stacked DIMM technology. Interesting technology that might provide an interesting glimmer of hope. Robert L, the answer to your question is not 100% clear, but falling much closer to ‘YES’. There are plenty of folks that preach “bandwidth, bandwidth, bandwidth.” This is very much true. You’re also correct that there doesn’t seem to be quantum leaps in memory bandwidth coming down the pipe in the near future. However, as bandwidth continues to creep up, we need to remember the ‘other’ memory performance factor: latency. The latency required to fetch a single cache line from a DRAM is reasonably high [as compared to cache and registers]. This latency has not improved over time at the same scale that transistor density has [eg, Moore's Law]. The moral of the story is, we need to spend more time focusing on the memory performance of applications and architectures. This story includes two main chapters: memory bandwidth and memory latency [how to cover latency with outstanding operations and reducing the latency with new technologies].

Do a google search on 3D Stacked DIMM technology. Interesting technology that might provide an interesting glimmer of hope.

]]> By: Robert L http://insidehpc.com/2010/07/29/tacc-on-memory-performance-in-a-cluster/#comment-242698 Robert L Fri, 30 Jul 2010 13:10:37 +0000 http://insidehpc.com/?p=12766#comment-242698 Weird. Did TACC fall asleep two years ago and just wake up last week? Intel was giving talks in its booth at SC'08 showing that WRF was 3x faster on Nehalem than on equivalently clocked Harpertown. My question is that with core counts continuing to climb, and without another quantum leap in memory bandwidth in sight, will we just find ourselves back in the Harpertown scenario in a year or two? A paper answering *that* question would be a paper worth reading. Weird. Did TACC fall asleep two years ago and just wake up last week? Intel was giving talks in its booth at SC’08 showing that WRF was 3x faster on Nehalem than on equivalently clocked Harpertown.

My question is that with core counts continuing to climb, and without another quantum leap in memory bandwidth in sight, will we just find ourselves back in the Harpertown scenario in a year or two? A paper answering *that* question would be a paper worth reading.

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