In this whitepaper, Intel engineers describe the challenges that tera-scale computing presents to the memory sub-system, such as performance metrics including memory bandwidth capacity and latency, as well as the physical challenges of packaging and memory channel design. New technologies that need to be developed and matured for tera-scale memory sub-systems are also discussed.
Tera-scale CPUs will demand a large amount of bandwidth from their memory sub-systems. Their demand for memory bandwidth will exceed one TBps. Current DRAM architectures and the DDR-based interfaces to those chips will not meet the needs of tera-scale CPUs. There is no simple solution to the challenges associated with bandwidth to memory; many aspects of the memory sub-system will require further research. Three key metrics have been identified that need improvement: bandwidth, power, and cost. There are strong dependencies between these metrics.
Intel asks for your name and email to download this 101-page paper, but it is very well-written and I highly recommend it.