AMD Fellow Tim Fisher writes about new details on the company’s pending Bulldozer architecture that will be revealed at this week at the International Solid State Circuits Conference (ISSCC) in San Francisco.
To quickly review, the centerpiece of the “Bulldozer” module is its two tightly-linked processor cores (Figure 1). These cores share several high-bandwidth resources (such as the Floating Point Unit) to provide chip-multithreading (CMT) which efficiently executes multiple instruction threads in parallel. Bulldozer’s CMT provides a marked design improvement over current threading approaches which either funnel multiple instruction threads through one processor core (SMT) or replicate cores statically (CMP) – approaches with inherent constraints and performance bottlenecks. Less visible, but just as important, Bulldozer also combines extensive improvements in silicon circuit design with an advanced 32nm Silicon-on-Insulator (SOI) process to provide significant advantages in power, performance, and reliability.