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Hybrid Memory Cube to Speed HPC

GigaStacey writes that Samsung and Micron are collaborating on a new type of memory chip designed for HPC. The two firms have formed the Hybrid Memory Cube Consortium to build a chip with 15x more memory bandwidth than current devices.

Some companies try to address the memory bandwidth problem by creating custom fabrics inside the chip to shuttle information around, while others basically create a giant caching system to pull information as rapidly as possible. The Hybrid Memory Cube guys are approaching it with density and a logic layer in a different type of architecture. The logic layer sits on the bottom, and the memory is densely stacked on top in a cube as opposed to a flatter architecture. Stacked memory isn’t new either, as startups and large chip firms like IBM have tried that approach — but such a radically new architecture as a densely stacked cube has its pros and cons.

The need to move data faster is a key issue for HPC today. While this specification is scheduled to come out in 2012, HP has its own plans in the works. This week Stan Williams, Senior Fellow at HP, told the IEF2011 in Seville that HP intends to have its mristor alternative technology to flash on the market in eighteen months, an alternative to DRAM in three to four years and, following DRAM, a replacement for SRAM.

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