Video: Intel's Knights Corner Does 1 Teraflop on a Single Chip at SC11

In this video, Intel’s Raj Hazra showcases the company’s new Knights Corner HPC platform, which is capable of 1 Teraflop of performance on a single chip.

Intel gave a three part story yesterday in their press luncheon. Two parts Intel MIC, one part Xeon Sandy Bridge.  Part 1, Intel reached an interesting milestone by demonstrating the first silicon of Knights Corner, running at a Teraflop of DGEMM.  (teraflop foil ASCI RED v KNC) This is news because it establishes that Intel, like Nvidia, will have a highly parallel optimized architecture that has solid performance for supercomputing applications.  Unlike GPU’s however, Intel promised to preserve the programming model of traditional clusters when MIC rolls out. Intel’s Robert Harrison presented the MIC programming model and then Jeff Nichols ORNL and Robert Glenn Brook from University of Tennessee discussed their experience porting 10’s of millions of lines of code to MIC over a few months.

To round things out, Hazra showed the performance of Xeon e5 processors (Sandy Bridge) on the Top500 list, and interestingly compared it versus the Top500 listings performance from AMD 6200 (Interlagos).

Knights Corner in its first weeks, is showing the kind of performance potential we hoped for when we introduced our Intel® MIC strategy at ISC10.” Hengeveld, HPC Segment Marketing Director.  “The  notion that these products are fully functional compute nodes that support MP, MPI, and standard languages has been proving out well at ORNL, TACC, Sandia, among others.. and we are excited to see our promises from last year turn into reality.”

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Comments

  1. John Hengeveld says:

    Robert Harrison was the speaker on the Intel MIC programming model :)

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