It’s clear to me that hybrid architectures make increasing sense in our power-constrained future, and Intel’s MIC effort shows they think so too. The upcoming Knights Corner processor will reportedly look much like today’s Fermi GPUs: power-efficient accelerators attached to an x86 CPU via PCIe. Programming the two architectures should be very similar: structure applications to expose parallelism and locality, and express via directives; use the multi-core CPUs for serial code, and execute the parallel kernels on the accelerator. The hope that unmodified HPC applications will work well on MIC with just a recompile is not really credible, nor is talking about ease of programming without consideration of performance.
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