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9 Petaflop Stampede Super Coming to TACC in January

Over at BSN, Theo Valich writes that Jay Boisseau’s presentation at the recent Intel Developer Forum sheds light on TACC’s plans to deploy the Stampede supercomputer powered by Xeon Phi co-processors.

The system originally targeted 10 PFLOPS, but it seems they might miss the mark by a few dozen/hundred TFLOPS. According to information given, the Stampede deploys 2 PFLOPS of compute power through Sandy Bridge-EP based Xeon CPUs and no less than 7 PFLOPS using Xeon Phi “coprocessors”. Even though TACC did not disclose how many thousands of Dell servers are being deloyed, we know that the supercomputer has 272TB of DDR3 memory and 14PB of total storage. The Xeon processor is E5-2680 (Sandy Bridge-EP), while TACC is using special versions of pre-production Xeon Phi processors in order to make the launch.

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