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TACC to Offer Training on Code Optimization for Intel Xeon Phi

As the first installation to deploy the new MIC technology at large scale in the forthcoming Stampede supercomputer, TACC and partners will soon begin offering training workshops, technical documentation, and academic content to help the research community rapidly develop applications using Intel’s new Xeon Phi coprocessors.

MIC’s support of standard programming languages and tools allow almost any code to be compiled for MIC and natively executed on MIC,” explained TACC research staff member Lars Koesterke. “In fact, since the Xeon Phi development environment supports native C/C++ and Fortran cross-compilation and direct login access to the coprocessor, the porting process is generally very straightforward.” Koesterke notes, however, that optimization efforts should still be considered after initial porting to maximize vectorization and parallel efficiencies on this new architecture. These are focus areas of early TACC training and documentation.

In December and January, leading up to the launch of Stampede on January 7, both TACC and Cornell will offer training, first to early users and then to anyone interested in learning about the new technology. Information from the training will be made available online, helping to prepare the research community for Stampede. This will be followed by a new course at The University of Texas at Austin on hybrid programming for heterogeneous systems like Stampede.

For more details, read the Full Story or check out the TACC booth #1511 at SC12.

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