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Fujitsu Develops 32 Gbps Transceivers for Inter-Processor Communications

This week Fujitsu Laboratories announced the development of transceiver circuits capable of communicating at 32 Gbps, a world record. The company said the new technology will support inter-processor communications at roughly twice today’s rates, leading to improved performance in next-generation of servers and supercomputers.

Figure 2: Schematic of transmitter circuit and breakdown of power consumption

Transmitter circuits transmit data from multiple channels that have been multiplexed into a single channel. The final-stage multiplexer not only consumes considerable amount of power, but also will approach the limit of its operating speed as data rates increase. Fujitsu Laboratories has developed a transmitter circuit that eliminates the need for a final-stage multiplex circuit (2-to-1 multiplexer). Rather than using conventional binary values (0, 1) in the transmitted signals, the new circuit uses ternary values (0, 1, 2). This makes it possible to restore the original data on the receiving end using only the existing receiver circuit functionality, without having to add any special circuitry (Figure 2, left). As a result, it exceeds the speed limit of conventional transmitter units. This is also why power consumption can be reduced by roughly 30% compared to the existing technology (Figure 2, right).

Details of the new technologies were presented at the IEEE International Solid-State Circuits Conference 2013 this week in San Francisco. Read the Full Story.

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