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PCIe 4.0 Specification Delay is Bad News for HPC

henry2Over at InfoStor, Henry Newman from Instrumental writes that another delay of the PCIe 4.0 specification is very bad news for HPC users. According to reports, the PCIe 4.0 specification is not going to be available until early-to-mid 2016.

So that means we can see PCIe 4.0 products in late 3Q16 or early 4Q16. This will be in time for 24 Gbit/sec SAS, but PCIe 4.0 will be very late for EDR InfiniBand and host side 100 Gbit ethernet. It’s easy, of course, for me to say just get it done, but these are hard problems. You have to integrate the PCIe channel such so that there is connectivity to memory to supply enough bandwidth. Today that number is 40 GB/sec and with PCIe 4.0 that will likely go to 80 GB/sec. Heck it was not but a few years ago that the memory bandwidth of a whole Xeon was less than 80 GB/sec, but as I have always said the issue is a balanced system. CPU performance has gone up, memory bandwidth has gone up both more than 8x since 2004, while I/O bandwidth in and out of the system has not. 80 GB/sec per bus is not going to be enough.

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