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Preparing for Advanced Manycore Architectures – and Implications on the Interconnect

In this video from the 2015 OFS Developer’s Workshop, Katie Antypas from LBNL presents: Preparing the Broad DOE Office of Science User Community for Advanced Manycore Architectures – and some implications for the interconnect. As part of the discussion, Antypas describes how NERSC is readying code for the Cori supercomputer based on Intel Knights Landing.

Our goal is to have over 10x performance, over our Hopper system – which is a petascale system. Cori will have about 50 cabinets. It will be composed of Intel Knights Landing processors. It’ll be a Cray system, so we’ll use the Cray Aries interconnect, and it’ll have a Dragonfly topology. We’re really very excited because it’s going to give us really a big boost in scientific capability over what we currently deploy. So 10x is kind of a baseline but we actually believe that we would be able to do much better than that. That would be a big boost for our scientists.

Antypas describes Cori as a “Pre-Exascale System.” To achieve performance goals, Cori users will need to modernize their code for the Knights Landing architecture.

We need to emphasize here that the Knights Landing processor is self-hosted, and so that means it’s not an accelerator. It’s not a coprocessor and the particular kernel processor that will be having for NERSC-8, will have more than 60 cores and it will have multiple hardware threads for the core. That’s a lot, right? Having 60 cores per node with multiple hardware threads. That a significant increase from both our Hopper and Edison system, which has 24 cores each. So we’re going to be working with our users to figure out what’s the right amount of parallelism that they need to expose in their application.

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