Colfax Research has published a new whitepaper entitled: Multi-Threading and Parallel Reduction. As part 1 of a 3-part educational series, the paper authored by Ryo Asai and Andrey Vladimirov focuses on optimization of applications for the Intel Xeon processors and Intel Xeon Phi coprocessors.
In this paper we focus on thread parallelism and race conditions. We discuss the usage of mutexes in OpenMP to resolve race conditions. We also show how to implement efficient parallel reduction using thread-private storage and mutexes. For a practical illustration, we construct and optimize a micro-kernel for binning particles based on their coordinates. Workloads like this one occur in such applications as Monte Carlo simulations, particle physics software, and statistical analysis. The optimization technique discussed in this paper leads to a performance increase of 25x on a 24-core CPU and up to 100x on the MIC architecture compared to a single-threaded implementation on the same architectures.