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ExaNeSt Technology: Targeting Exascale in 2018

In this video from the Disruptive Technologies session at the 2015 HPC User Forum, Peter Hopton from Iceotope presents: ExaNeSt technology: Targeting Exascale in 2018.

ExaNeSt will develop, evaluate, and prototype the physical platform and architectural solution for a unified Communication and Storage Interconnect and the physical rack and environmental structures required to deliver European Exascale Systems. The consortium brings technology, skills, and knowledge across the entire value chain from computing IP to packaging and system deployment; and from operating systems, storage, and communication to HPC with big data management, algorithms, applications, and frameworks. Building on a decade of advanced R&D, ExaNeSt will deliver the solution that can support exascale deployment in the follow-up industrial commercialization phases. Using direction from the ETP4HPC roadmap and soon-available high density and efficiency compute, we will model, simulate, and validate through prototype, a system with:

  1. High throughput, low latency connectivity, suitable for exascale-level compute, their storage, and I/O, with congestion mitigation, QoS guarantees, and resilience.
  2. Support for distributed storage located with the compute elements providing low latency that non-volatile memories require, while reducing energy, complexity, and costs.
  3. Support for task-to-data sw locality models to ensure minimum data communication energy overheads and property maintenance in databases.
  4. Hyper-density system integration scheme that will develop a modular, commercial, European-sourced advanced cooling system for exascale in ~200 racks while maintaining reliability and cost of ownership.
  5. The platform management scheme for big-data I/O to this resilient, unified distributed storage compute architecture.
  6. Demonstrate the applicability of the platform for the complete spectrum of Big Data applications, e.g. from HPC simulations to Business Intelligence support.

exanestAll aspects of ExaNeSt will be steered and validated with the first-hand experience of HPC applications and experts, through kernel turning and subsequent data management and application analysis.”

View the Slides

See more talks from the HPC User Forum

In related news, the HPC User Forum has posted their Agendas for upcoming meetings in Europe:

  • GENCI will host the HPC User Forum in Paris Oct. 12-13. The Agenda includes speakers from Airbus, GENCI, Renault, and NASA. The meeting is free to attend. Register now.
  • LRZ will host the HPC User Forum in Munich Oct 15-16. The Agenda includes speakers from LRZ, CSCS, DKRZ, Paypal, and the Gauss Centre for Supercomputing. The meeting is free to attend. Register now.

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