Today Cadence Design Systems announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing platforms. As a result of the joint work, Cadence digital, signoff and custom/analog tools have achieved certification for the latest Design Rule Manual (DRM) and SPICE for the TSMC 7nm process. In addition, a new process design kit (PDK) enabling customers to achieve optimal power, performance and area (PPA) is now available.
TSMC’s process innovations require ongoing tool and IP enhancements so that we can deliver optimal solutions for advanced-node customers,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “Our joint work supports the needs of early customers who are transitioning to the 7nm node to maintain leadership in the mobile and HPC markets.”
Cadence has also made enhancements to the 7nm Custom Design Reference Flow and library characterization flow. These design tool advancements have enabled Cadence to accelerate initial deliveries of its high-speed SerDes and low-latency DDR IP cores to leading customers, with test chips expected to tape out in the fourth quarter of this year. These products represent the first of a comprehensive portfolio of application-optimized 7nm solutions to be developed by Cadence.
Working together, Cadence and TSMC have developed some of the first design IP offerings for the 7nm process, offering early IP access to protocols that are optimized for and most relevant to mobile and HPC applications. Simulations of Cadence’s high-speed SerDes and low-latency DDR IP initial customer deliveries indicate a 50 percent power reduction and a 35 percent speed gain compared to TSMC’s 16nm process technology. These early 7nm SerDes and DDR deliveries represent the first of a comprehensive portfolio of Cadence 7nm solutions.
We worked closely with Cadence to certify the tools and integrated flow for 7nm designs, which will help customers achieve PPA objectives and create designs with confidence,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By working together with Cadence, we are able to actively engage with customers on advanced 7nm designs to enable them to maximize the benefits of this leading-edge technology.”