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Nvidia’s Bill Dally to Keynote HiPINEB 2017 Exascale Workshop

Bill Dally, Nvidia Chief Scientist and Senior Vice President of Research

Bill Dally, Nvidia Chief Scientist and Senior Vice President of Research

Nvidia’s Bill Dally will keynote HiPINEB 2017 – the 3rd IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era. The event takes place Feb. 5, 2017 in Austin, Texas and will be held in conjunction with the IEEE HPCA Conference.

By the year 2023, HPC Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or increases marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands. Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network becoming the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc.

The main goal of the third edition of HiPINEB is to gather and discuss in a full-day event the latest and most prominent efforts and advances, both from industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands.

In related news, the deadline for paper submissions has been extended to Dec. 7, 2016.

All researchers and professionals, both from industry and academia, working in the area of interconnection networks for scalable HPC systems and Datacenters are encouraged to submit an original paper to the workshop and to attend this event.

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