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HiPINEB Workshop on High Performance Networks Posts Agenda for February 5 in Austin

The IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB) has published its program agenda. Held in conjunction with the IEEE HPCA 2017 Conference, HiPINEB takes place Feb 5, in Austin, Texas.

By the year 2023, High-Performance Computing (HPC) Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or increases marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands. Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network becoming the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc.

The main goal of the third edition of HiPINEB is to gather and discuss in a full-day event the latest and most prominent efforts and advances, both from industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands.

Speakers include:

  • Pedro Javier Garcia, University of Castilla-La Mancha, Spain
  • Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain
  • Francisco J. Quiles, University of Castilla-La Mancha, Spain
  • Bill Dally, Chief Scientist and SVP of Research in NVIDIA, and Stanford Professor
  • Dave Mayhew, San Diego University, USA
  • Bill Dally, NVIDIA and Stanford University, USA
  • Torsten Hoefler, ETH Zurich, Switzerland
  • Mariano Benito, Enrique Vallejo, Ramón Beivide and Cruz Izu (University of Cantabria, Spain, and The University of Adelaide, Australia)
  • Matthieu Pérotin and Tom Cornebize (Atos, France, and ENS Lyon, France)
  • Junhyun Shim, Joongi Kim, Keunhong Lee and Sue Moon (SAP Labs Korea, Lablup Inc. and KAIST, South Korea)

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