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European Teams to Face Off in ISC’13 Klusterkampf

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Over at the Student Cluster Competition Blog, Dan Olds writes that the first Battle of Liepzig in 1813 can’t really compare to what’s coming in June: The Second Battle of Leipzig, aka the ISC’13 Klusterkampf. Now in its second year, the ISC Student Cluster competition will feature nine teams of university undergrad students in a quest to build the fastest supercomputer on the show floor.

Chemnitz University of Technology is only 51 miles from Leipzig and thus the hometown favorite. The school, founded in 1836, was a fast starter in terms of science and technology. During one pre-1900 period, Chemnitz generated more patent registrations than any other institution in the world. Currently, the university is ranked near the top of German technical schools, a reputation they’ll be putting on the line at the student cluster challenge. Judging by their entry application, Chemnitz (or TUC, which stands for Technische Universitat Chemnitz) has a deep HPC curriculum, including courses and research on FPGA and GPU application acceleration. Team TUC has partnered with German hardware vendor MEGWARE GmbH to build “TurboTUC,” the schlachtkreuzer they hope to ride to victory.

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Video: The New Style of IT – HP Moonshot Update for Moabcon 2013

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In this video from Moabcon 2013, Dick Bland and Jérôme Labat from HP present: The New Style of IT: HP Update for Moabcon 2013.

Cloud, Mobility, Security, and Big Data are transforming what the business expects from IT resulting in a “New Style of IT.” The result of alternative thinking from a proven industry leader, HP Moonshot is the world’s first software defined server that will accelerate innovation while delivering breakthrough efficiency and scale.

While the first spin of Moonshot is not targeted at HPC, Bland said that HP will be able to spin up new modules for the platform that could include FPGAs and ARM-based nodes more suited to high performance computing.

View the Slides on Slideshare.

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Podcast: Radio Free HPC Looks at FPGAs

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In this podcast, the Radio Free HPC team discusses the recent buzz surrounding FGPAs. After being sidelined by accelerators, they’re increasingly being used in appliances.

Big vendors are talking about FPGAs not only for appliances but for general-purpose systems as performance assists. Are we headed back to the future? The guys discuss the ins and outs of FPGAs and why, in some cases, they could be a huge win for the organizations that implement them. But is the architecture flexible enough? For enterprise and Big Data, perhaps it is. If you need to perform the same algorithms over and over again, FPGAs could be a perfect fit. As with all things tech, there are a few cautionary notes to be sounded. Amassing more and more appliances can lead down a tricky road. Will their use in workload-optimized systems lead to vendor lock-in? Can you really teach an old FPGA new tricks? And can they be weaponized?

Most importantly: how are servers like cattle? Tune in to find out…

Download the MP3 * Subscribe on iTunes * RSS Feed

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Hybrid CPU-GPU Chips Plus RDMA and PCI-Express Make for Screamin’ Iron

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Over at The Register, Timothy Prickett Morgan writes that a GE presentation at the recent GPU Technology Conference discussed the benefits of Remote Direct Memory Access (RDMA) for InfiniBand and its companion GPUDirect method of linking GPU memories to each other across InfiniBand networks.

On plain old CPUs, RDMA allows CPUs running in one node to reach out through an InfiniBand network and directly read data from another node’s main memory, or push data to that node’s memory without having to go through the operating system kernel and the CPU memory controller. If you prefer 10 Gigabit Ethernet links instead, there is an RDMA over Converged Ethernet, or RoCE, wrapper that lets RDMA run on top of Ethernet – as the name suggests. With GPUDirect, which is something that InfiniBand server adapter and switch maker Mellanox Technologies has been crafting with Nvidia for many years, the idea is much the same. Rather than having a GPU go back to the CPU and out over the network to get data that has been chewed on by another GPU, just let the GPUs talk directly to each other over InfiniBand (or Ethernet with RoCE) and get the CPU out of the loop.

GE's IPN251 hybrid computing card marries a Core i7, a Xilinx FPGA, and an Nvidia Kepler GPU with a PCI switch

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ISC’13 Preview: The Role of HPC in Oil and Gas

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Head of the Fraunhofer Competence Center for HPC at the Fraunhofer ITWM, Dr Franz-Josef Pfreundt is scheduled to host a session on oil and gas at ISC’13. Beth Harlen caught up with him to find out more.

Dr. Franz-Josef Pfreundt

At ITWM, I founded departments that focus on image analysis, flow in complex media, and high-performance computing (HPC), which aid the development of simulation software. At the university in the late 1980s, we were developing software for the re-entry simulations for the European space shuttle and, as you can imagine, this was a very time -consuming process. We were looking for faster systems at a time when the first parallel machines were beginning to emerge, and I do believe that we were the first group in Germany to purchase an nCube parallel machine. Using parallel machines for very compute-intensive simulations is where my interest in HPC began.

 

My involvement with ISC started in the early 1990s, and I will be chairing the session on oil and gas at this year’s event. ITWM works closely with many oil and gas companies to develop seismic imaging software that aims, among other things, to improve the understanding of sub-surface structures. Oil and gas is one of the fields today where huge compute capacities are needed and increasingly being sought. If you look around the industry, you see that companies like Total are investing in HPC systems – such as Pangea, the petaflop system it recently purchased – because the problems they face are so large and compute-intensive, they would be impossible to tackle without such resources.

The session at ISC will focus on the question of what the oil and gas industry is doing with HPC, with secondary topics that look at the algorithmic challenges and HPC challenges behind that. The fact that algorithms need to be tailored to certain machines has prompted accelerator discussions in the industry, revolving around FPGAs, GPUs, Intel Mic, etc. We now have to question what the right CPU for the right algorithm is, and vice versa. As machines become faster, we also have the opportunity to address whether methods that were too challenging for previous systems can now be applied.

The development of software costs a considerable amount of money and can easily take years before developers have anything productive. Then there is the architecture to consider – so the first step is to look for mainstream architecture to make the code work, and then determine what new technologies to invest in, depending on the algorithm. One of the main workhorses in seismic imaging today is the Revers Time Migration. The oil and gas industry is using both CPUs and GPUs to solve this problem. In the isotropic case, GPUs have no advantage but in stronger anisotropic cases GPUs are faster. GPUs’ architectures are changing and so has the code, so from a software developers’ point of view it is not an easy choice.

Opinions on accelerators can differ greatly – which is why I will be stimulating the discussion during my session at ISC. The views and investments in the oil and gas industry are important not only for scientists and vendors involved in that sector, but for HPC in general. ISC provides a good forum for discussion as there is always enough time to meet people and follow up on discussions that have been sparked by the sessions or presentations.

The combination of conferences and exhibitions works well for me as an attendee and ISC’13 will be offering an increased parallel research track, with many scientific papers being presented. I think this is an important development for ISC because it is assimilating elements of scientific conferences while maintaining its focus on academia and application. It’s this exploration of what we as an industry can do with the theoretical that makes trade shows like this so valuable.

This story appears here as part of a cross-publishing agreement with Scientific Computing World.

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Interview: EXTOLL to Demo Ultra-Low-Latency Interconnect at ISC’13

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It has been a while since the folks from the EXTOLL project in Germany announced their venture to develop an ultra-low latency interconnect technology for supercomputing. With ISC’13 coming up, I caught up with R. Mondrian Nuessle from Extoll to discuss their plans for the technology and their exhibit at ISC.

insideHPC: What is the EXTOLL interconnect and who is the target user of this technology?

Mondrian Nuessle: The EXTOLL interconnect technology was specifically developed for High Performance Computing. It aims at minimizing the communication overhead between nodes by optimizing the whole communication stack from the physical layer all the way up to the application interfaces like MPI.

insideHPC: How does EXTOLL differ from commodity technologies currently available out there?

Mondrian Nuessle: EXTOLL technology tops commodity technologies by virtually all metrics relevant for HPC including latency, message rate, and bandwidth. Users’ benefit depends on the particular application, but typically a speed up by a factor of 2 will be experienced. This is achieved by an ultra low latency of 600ns, a message rate of more than 100 million messages per second and a bandwidth of 120 Gb/s per link. Each host adapter features 6 bi-directional links of 120Gb/s each, as well as an integrated low-latency message router.

To form an EXTOLL network, EXTOLL adapters are plugged directly together forming for example a 3D torus topology. Thus, the EXTOLL interconnect technology is designed to be a direct network rendering external switches obsolete. This alone will allow customers to realize significant OPEX and CAPEX savings. The EXTOLL interconnect also implements a lot of different technologies to optimally support HPC work loads. Amongst them are low-latency messaging services, high-bandwidth bulk transfers, hardware implemented barriers and multicast, deterministic and adaptive routing, a large amount of reliability features and many more. In summary, the EXTOLL technology is optimized for HPC from the start with no trade-offs! This enables customers to close the gap between commodity clusters and dedicated MPP HPC systems. So in one sentence one can say, by using EXTOLL technology users will get the features, performance and benefits of MPPs for the price tag of commodity clusters.

insideHPC: Does your software stack support MPI? Will your software be open source?

Mondrian Nuessle: Yes, of course. The EXTOLL software stack supports MPI as a “premiere citizen”. From an OS perspective, EXTOLL will focus on Linux first. Linux kernel drivers as well as the low-level API libraries and the MPI integration will be released as open-source. One of the first MPI distributions that will be supported is OpenMPI.

But the EXTOLL software is not uniquely focused on MPI. Support for other communication middlewares and runtimes is under development. An example is GASNET. TCP/IP transport service will be available, too.

insideHPC: Are you still in the prototype stage or is the technology currently available?

Mondrian Nuessle: The EXTOLL ASIC is just in the tape-out stage. First silicon will be available around mid of 2013. Prototypes are based on FPGAs and are fully functional. These prototypes including the beta software stack are out in the field and show performance that is comparable to leading commodity products in many regards, although the raw punch of the FPGA is at least a factor of 4 less than the targeted ASIC technology.

insideHPC: What will you be showcasing at your booth during ISC’13?

Mondrian Nuessle: First of all we will be demonstrating the EXTOLL interconnect with industry standard servers in cooperation with Thomas Krenn AG and NVIDIA. One other thing we will be showing is EXTOLL’s direct GPU-to-GPU communication. One GPU directly communicates with and accesses the memory of a second GPU via the EXTOLL network without involving the host CPUs. This dramatically improves Inter-GPU communication, with savings in energy and time. This new technique is in particular useful with recent Nvidia features like Dynamic Parallelism and GPUDirect RDMA. It addresses the increasing use of accelerators in HPC.

We will also be presenting our 12x active optical cables (AOC). This cable features an electrical connector that can be plugged directly into any electrical connector of EXTOLL cards. Depending on the length of links, users can choose to use EXTOLL AOC or electrical cabling. Moreover, EXTOLL is used within the EU funded FP7 Project DEEP for the BOOSTER interconnect and first BOOSTER node hardware will be presented in cooperation with Eurotech at the Eurotech booth and at the booth of the Jülich Supercomputing Center (JSC).

insideHPC: Why is ISC’13 an important event for you as you commercialize this company?

Mondrian Nuessle: The best way to commercialize a new product or even a company is to be at the right place at the right time. ISC is definitely among the “hot” places for HPC. There is a perfect opportunity to meet trade partners, get their personal feedback, initialize/continue negotiations and become aware of upcoming developments. While SC is the premier venue for the US market, ISC is inevitable to talk to European custmers and partners. And for EXTOLL as a German company, we are especially happy to be able to attend this event in Germany.

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Matrox Rolls Out Hybrid Supersight Solo HPC Platform

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Today Matrox announced a low-cost addition to its Supersight family of industrial imaging computers that leverage the power of multi-core CPU, GPU, and FPGA technologies. Available in a 4U chassis, the news Matrox Supersight Solo lets OEMs and systems integrators maximize compute density in a 4U chassis with up to thirteen PCIe 2.0 x16 slots and dual PCIe 2.0 x16 host interfaces.

This new addition to the Matrox Supersight™ family lets developers design cost-effective imaging systems using a lifecycle managed platform that minimizes the need for revalidation and provides consistent long term availability,” said Michael Chee, product manager at Matrox Imaging. “We have also taken the occasion of this new product introduction to pass along recent production cost savings on the original, multi-node Supersight, which reduce the price by over 25%.”

The new Matrox Supersight Solo systems will be available in Q2 2013. Read the Full Story.

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Video: Fabrics and Interconnects Session at Hot Chips 2012

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In this video, the Hot Chips 2012 conference holds a session on Fabrics and Interconnects.

You can also check out the rest of the Hot Chips 24 sessions.

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Solarflare ApplicationOnLoad Engine – HPC Processing on a “Bump in the Wire”

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In this video from SC12, Solarflare CEO Russell Stern describes the company’s new “bump in the wire” ApplicationOnLoad Engine (AOE). By enabling applications to be processed on the fly right on the NIC server adapter, the company is opening up a new paradigm of computation, ransforming the way networks process data and overcoming performance obstacles that cannot be solved by simply adding more processors.

Leveraging our high-performance 28-nm Stratix V FPGA, Solarflare has created a comprehensive firmware development kit that provides a straightforward integrated application development environment,” said Jeff Waters, senior vice president and general manager of the Military, Industrial and Computing Division of Altera. “With its ApplicationOnLoad Engine, Solarflare is delivering an integrated application on-load solution that enables application processing to be moved directly to the network adapter for lower latency, CPU offload or compliance.”

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Solarflare Rolls Out University Program for ApplicationOnLoad Engine

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This week Solarflare, the leader in application-intelligent 10GbE networking software and hardware, announced the launch of its Solarflare University Program for the Solarflare ApplicationOnLoad™ Engine (AOE). Providing access to the AOE hardware and development kits at a substantial educational discount allows the Solarflare University Program to offer FPGA-based products for classroom instruction in computer science and computer engineering and helps to pioneer advances in Customized Compute. Solarflare also announced the Innovation Awards to encourage and reward research, innovation, and application development in the field of Customized Compute.

The Solarflare University Program and the Innovation Awards are examples of how private industry and universities can work together to better educate our students about new technologies and equip them with the latest tools and knowledge,” said Melissa Smith, assistant professor, Holcombe Department of Electrical and Computer Engineering at Clemson University. “The Future Computing Technology Laboratory at Clemson University is dedicated to research in reconfigurable computing and providing our researchers and students with an advanced computing infrastructure [and] we look forward to working with Solarflare and being a part of the University Program.”

Come by the Solarflare booth #3754 at SC12. Read the Full Story.

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Energy Efficiency Focus in the SC12 Technical Program

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Energy Efficiency Focus in the SC12 Technical Program

by Natalie Bates, Co-chair Energy Efficient HPC Working Group (EE HPC WG)

 

Energy efficiency will again be a hot topic at SC12, with at least 38 Technical Program sessions focused on energy efficiency.  A complete list of these sessions organized both chronologically and by topic can be found on the Energy Efficient HPC Working Group website.  SC12, the annual International Conference for High Performance Computing, Networking, Storage and Analysis, will be held Nov. 10-16 in Salt Lake City, Utah. For more information, see the SC12 website.

BROAD SCOPE SESSIONS

The Third Annual Workshop on Energy Efficient High Performance Computing – Redefining System Architecture and Data Centers” promises to be interesting to a broad audience.  Some of the featured speakers include; Peter Kogge, University of Notre Dame who will look at the historical trends of power, energy and supercomputing; John Shalf, Lawrence Berkeley National Laboratory whose talk will focus on the energy requirements for applications; as well as Herbert Huber, Leibniz Supercomputing Center and Steve Hammond, National Renewable Energy Laboratory who will speak about energy efficient data centers.

There are four other technical programs that will cover the topic of energy efficiency at a high level.  Kirk Cameron, Virginia Tech is on the slate to give two talks, both of which have clever and enticing titles with phrases about a “Growing Power Struggle” and “Energy Oddities.”  Prohibitive energy costs motivated Thomas Ludwig, German Climate Computing Center to consider the cost and benefits of “HPC-Based Science in the Exascale Era.”  Finally, there is a “Cool Supercomputing” Birds of Feather (BoF) organized by Pacific Northwest National Laboratory that covers tools and techniques for optimizing energy consumption at all levels.

Setting Trends for Energy Efficiency” is a BoF representing a collaborative effort by the Top500, Green500, the Energy Efficient HPC Working Group and The Green Grid to standardize the power measurement methodology used when running system workloads for architectural comparison, such as High Performance Linpack.  This is one of seven sessions that cover energy efficiency measures and metrics.  The Green500, Top500 and now the Graph500 have their own BoFs and will report power consumption and energy efficiency as well as performance for their Lists.   The High Performance Group  at at the Standard Performance Evaluation Corporation (SPEC) has also organized a BoF that will discuss  a new OpenMP benchmark suite with an optional energy metric that scales to 512 threads.  From the home of the Green500 at Virginia Tech, Balaji Subramaniam will present his doctoral showcase on metrics for energy efficiency.  Finally, an Intel team will present a paper on tuning for the Graph500 Traversal which includes both performance and energy efficiency results.

SESSIONS FOCUSSED ON SYSTEM HARDWARE

Thirteen of the sessions are exploring system hardware energy efficiency.  Of these thirteen, seven of them focus on alternative processors like GPU and ARM that are continuing the trend towards aggregating low-power processors and using accelerators. There are three BoFs that explore alternative processors and all three are organized by Europeans. The Partnership for Advanced Computing in Europe (PRACE) explores a set of prototypes to test and evaluate promising new technologies for future multi- Petaflop/s systems that include GPUs, ARM processors, DSPs and FPGAs.  The Barcelona Supercomputing Center is heading up an ARM-based exascale demonstration and will review their research results and plans at two BoFs; “Energy Efficient HPC” and “Exascale Research- The European Approach.” Besides these BoFs, there is a session as part of Broader Exchange where Calxeda, an ARM-based server provider, will present their products and roadmaps.  NEC is presenting an exhibitor forum on “Hybrid Solutions with a Vector-Architecutre for Efficiency.”  There is also a paper on “Multi-Core DSP” and a poster on modeling “Power-Performance Efficiency” for GPUs.

A new topic for SC this year is a focus on memory technologies, which was presaged by a keynote at the International Supercomputing Conference held in Hamburg, Germany last June when Dr. Byungse So, Samsung Senior Vice President gave a talk on “Advanced Memory Technology – #1 Factor for Energy Efficient HPC”.  Two papers, RAMZzz and Mage, both explore novel memory system designs.  Samsung and Micron, respectively are presenting exhibitor forums on “How Memory and SSDs can Optimize Data Center Operations” and “Hybrid Memory Cube (HMC)”.

Whereas memory is on the uptake, the focus on liquid cooling has waned with only two sessions this year compared to six last year at SC’11.  Eurotech will present an exhibitor forum on “Differences Between Cold and Hot Water Cooling on CPU and Hybrid Supercomputers” and Green Revolution Cooling will present on “100% Server Heat Recapture in Data Centers is Now a Reality.”

DATA CENTER SESSIONS

Kimberly Cupps, Lawrence Livermore National Laboratory will present on “The Sequoia System and Facilities Integration Story”.  It appears that she will be giving the same talk at two different sessions; on Monday during Broader Engagement as well as on Tuesday as an Invited Speaker.  Also, the M+W Group will present an exhibitor forum on “Reducing First Costs and Improving Future Flexibility in the Construction of High Performance Computing Facilities.”

APPLICATION TUNING AND JOB SCHEDULING

There are nine sessions that describe research on tuning applications for energy efficiency and various aspects of energy efficient job scheduling.  Seven of the nine sessions are doctoral showcases, papers or posters.  There is a BoF on “Power and Energy Measurement Modeling”.  In this BoF, members of the research community and industry will present current state-of-the-art and limitations in measuring and modeling power and energy consumption and their effect on HPC application performance. An open discussion about future directions for such work will follow, with the intention of creating a “wish list” of feature requests to HPC vendors.  Another BoF of interest is the SLURM User Group Meeting, which provides an open source job scheduler.  Also, Charles Lively, ORNL will give a talk during Broader Engagement on “Heading Towards Exascale – Techniques to Improve Application Performance and Energy Consumption Using Application-Level Tools”.

Following is a list of the titles for the doctoral showcases:

Following is a list of the titles for the papers:

Following is a list of the titles for the posters:

OTHER SESSIONS

Two other sessions that will cover energy efficiency include an all day workshop on “High Performance Computing, Networking and Analytics for the Power Grid” and a poster on “Pay as You Go in the Cloud: One Watt at a Time.”

Although this is a list of sessions with a specific focus on energy efficiency, many more sessions will include energy efficiency as part of a broader focus.

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IBM PureData System a Pure Play for Big Data

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In this video, IBM’s Inhi Cho Suh, Vice President Product Management & Strategy, give a guided tour of the IBM PureData Systems, which are specifically designed to “efficiently manage and quickly analyze petabytes of data in minutes.” The company is offering three workload-specific models of the PureData System for Transactions, Analytics, and Operational Analytics.

So what is a PureData system in terms of architecture? Building off its Netezza platform that IBM acquired in 2010, the PureData is an “Expert Integrated System” that leverages FPGAs for specific tasks.

The PureData System’s orders-of-magnitude performance advantage over other analytic options comes from its unique asymmetric massively parallel processing (AMPP) architecture that combines open, IBM blade servers and disk storage with IBM’s patented data filtering using field programmable gate arrays (FPGAs). This combination delivers blistering fast query performance on analytic workloads supporting tens of thousands of BI and data warehouse users, sophisticated analytics at the speed of thought, and petabyte scalability.

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insideHPC at Hot Interconnects 2012

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Hot Interconnect 2012 Presentation Videos

insideHPC provided onsite coverage of Hot Interconnects 2012 in Santa Clara.

    • Caliper – Precise and Responsive Traffic Generator
    • Posted: 2012-08-27 01:02:28 UTC
      In this video, Yashar Ganjali from the University of Toronto presents: Caliper – Precise and Responsive Traffic Generator. “This paper presents Caliper, a highly-accurate packet injection tool that generates precise and responsive traffic. Caliper takes live packets generated on a host computer and transmits them onto a gigabit Ethernet network with precise inter-transmission times. Existing software traffic generators rely on generic Network Interface Cards which, as we demonstrate, do not provide high-precision timing guarantees. Hence, performing valid and convincing experiments becomes difficult or impossible in the context of time-sensitive network experiments. Our evaluations show that Caliper is able to reproduce packet inter-transmission times from a given arbitrary distribution while capturing the closed-loop feedback of TCP sources. ” Recorded at the Hot Interconnects 2012 conference in Santa Clara. http://hoti.org
    • Weighted Differential Scheduler

      Posted: 2012-08-27 00:58:48 UTC
      In this video, Hans Eberle from Oracle Labs presents: Weighted Differential Scheduler. “The Weighted Differential Scheduler (WDS) is a new scheduling discipline for accessing shared resources. The work described here was motivated by the need for a simple weighted scheduler for a network switch where multiple packet flows are competing for an output port. The scheme can be implemented with simple arithmetic logic and finite state machines. We are describing several versions of WDS that can merge two or more flows. An analysis reveals that WDS has lower jitter than any other weighted scheduler known to us.” Recorded at the Hot Interconnects Conference 2012 in Santa Clara. http://hoti.org
    • Performance Analysis of InfiniBand FDR and 40GigE RoCE on HPC and Cloud Computing Systems

      Posted: 2012-08-26 17:03:43 UTC
      In this video, Jerome Vienne from Ohio State University presents: Performance Analysis and Evaluation of InfiniBand FDR and 40GigE RoCE on HPC and Cloud Computing Systems. “In this paper, we evaluate various high performance interconnects over the new PCIe Gen3 interface with HPC as well as cloud computing workloads. Our comprehensive analysis, done at different levels, provides a global scope of the impact these modern interconnects have on the performance of HPC applications and cloud computing middlewares. The results of our experiments show that the latest InfiniBand FDR interconnect gives the best performance for HPC as well as cloud computing applications.” Recorded at Hot Interconnects 2012 in Santa Clara. http://hoti.org
    • Networks: How to Compare Alternative Architectures

      Posted: 2012-08-27 23:22:05 UTC
      In this video, Radia Perlman from Intel presents: How to Compare Alternative Architectures. “There are various aspects of network infrastructure that are orthogonal, and therefore can be compared conceptually. For example, the syntax of encapsulation, how forwarding tables are calculated, and whether forwarding tables are filled in proactively, or on-demand when a new flow starts. This talk will explain these concepts, and show how various proposed architectures (such as TRILL, VXLAN, OpenFlow, etc. compare.)” Recorded at the Hot Interconnects 2012 Conference. http://hoti.org http://hoti.org
    • Call for Participation in Small Business Technology Transfer (STTR)

      Posted: 2012-08-26 17:22:42 UTC
      Got Exascale ideas? In this video, Thomas Ndousse-Fetter from the DoE Department of Science announces a Call for Participation in the Small Business Innovation Research (SBIR) and Small Business Technology Transfer (STTR) programs. The program is for small businesses that want to get involved in the Exascale technology development ecosystem. “A Technology Transfer Opportunity (TTO) is an opportunity to leverage technology that has been developed at a DOE National Laboratory. Each TTO will be described in a particular subtopic and additional information may be obtained by using the link in the subtopic to the DOE National Laboratory that has developed the technology. Typically the technology was developed with DOE funding of either basic or applied research at a DOE National Laboratory and is available for transfer to the private sector. The level of technology maturity will vary and applicants are encouraged to contact the appropriate Laboratory prior to submitting an application.” Learn more about the program at: http://science.energy.gov/sbir/ Recorded at the Hot Interconnects 2012 Conference. http://hoti.org
    • Power-Efficient, High-Bandwidth Optical Interconnects for High Performance Computing

      Posted: 2012-08-25 16:54:07 UTC
      In this video, Fuad Doany from IBM T. J. Watson presents: Power-Efficient, High-Bandwidth Optical Interconnects for High Performance Computing. “High performance computing systems are driving development and large-scale deployment of parallel optical interconnects to meet the ever-increasing interconnect bandwidth requirements. We have demonstrated generations of chip-scale transceivers, or “Optochips”, with record setting high-speed, high-density, and low-power performance. Optical interconnects and Si-photonic communication still present significant technical challenges for future exa-scale supercomputers. Optical interconnect technology must continue to evolve to meet future bandwidth demand, including order of magnitude improvements in cost, power, density, and reliability. Integrated low-power parallel transceivers, optical printed circuit boards and silicon based integrated photonics are potential technologies to meet these challenges.” Recorded at the Hot Interconnects 2012 Conference. http://hoti.org
    • Electronic-Photonic Integration within Switches and Routers

      Posted: 2012-08-25 15:35:36 UTC
      In this video, Michael R. Watts from MIT presents: Electronic-Photonic Integration within Switches and Routers. “We review recent successes in silicon photonics and how the new capabilities afforded by silicon photonics will impact future Ethernet, Infiniband, and ultimately optical domain switches and routers. Specifically, we consider the impact silicon photonics can have on the cost, bandwidth, radix, and power consumption scaling of future switches and routers.” Recorded at the Hot Interconnects 2012 conference in Santa Clara. http://hoti.org
    • How SDNs Will Tame Networks

      Posted: 2012-08-25 20:04:39 UTC
      In this video, Nick McKeown from Stanford presents: How SDNs Will Tame Networks. “Networks are notoriously hard to debug. Today, we only have a rudimentary set of tools available, such as ping, traceroute, tcpdump, and netflow. These tools try to reconstruct the distributed state of the network in an ad-hoc fashion, while the state is being constantly changed by a variety of complex distributed protocols. Software-Defined Networks (SDNs) make it possible – for the first time – to verify, validate, and even prove that the network is behaving correctly. SDN provides the opportunity to rethink how we write network control programs, from the development of control programs all the way to their deployment in production networks.” Recorded at the Hot Interconnects 2012 conference in Santa Clara. http://hoti.org
    • Cray High Speed Networking

      Posted: 2012-08-25 08:11:01 UTC
      In this video, Cray’s Bob Alverson presents: Cray High Speed Networking. “This talk gives an overview of high speed interconnects across all of Cray’s products. Going back to the Seastar router, Cray has a torus network with high bandwidth. When combined with massively multithreading technology in uRiKA, Seastar provides direct load and store support that is unmatched today using commodity processors, especially on Big Data graph problems. The Gemini router introduced support for fine-grained load and store without requiring a custom processor. Our next generation router, known as Aries, brings that technology to the PCI Express bus, so that it can operate with a much wider range of processors. With Aries, the network topology is revamped to take best advantage of fiber optic links, which much be used for all but the shortest connections. The result is the dragonfly technology, providing high neighbor bandwidth to a large group of processors and configurable global bandwidth for system wide communication.” Learn more at: http://hoti.org
    • The Future Of Network Technology – What is Old, is New Again

      Posted: 2012-08-27 10:40:28 UTC
      In this video, the Hot Interconnects 2012 conference kicks off with a keynote by John Roese, VP and General Manager of Futurewei, Huawei’s North American R&D organization. “Cloud, SDN, Big data, Mobility, BYOD, etc… We are currently in an industry filled with major new technologies and architectures and each of them looks like a green field of innovation. The problem is that we have been here before many times. Our industry operates in cycles and many of the challenges we are taking on technically today at a component, system and solutions level are not as new as we like to think. As the former CTO or Nortel, Broadcom ENG, Enterasys and Cabletron over the past 20 years, I have seen these cycles and hopefully learnt some lessons. This talk will attempt to call out some of the similarity of current technical challenges with past technology work and industry efforts (some succeeded and some failed) in an effort to remind us all of our past experiences and hopefully use that history to better navigate the current challenges.” Learn more at: http://hoti.org
    • The OpenOnload User-level Network Stack

      Posted: 2012-08-23 15:07:21 UTC
      In this video, Dave Parry from SolarFlare presents: The OpenOnload User-level Network Stack. “This talk presents the OpenOnload architecture for user-level networking, which is rapidly becoming the de-facto standard for user-space protocol processing of TCP and UDP particularly in latency sensitive applications for the financial markets. We describe our solutions to the challenges outlined above, performance measurements and real world deployment-cases.” Learn more at http://solarflare.com and http://hoti.org
    • Rx Stack Accelerator for 10 GbE Integrated NIC

      Posted: 2012-08-23 06:45:23 UTC
      In this video, IBM’s François Abel presents: Rx Stack Accelerator for 10 GbE Integrated NIC. Recorded at the Hot Interconnects 2012 conference in Santa Clara. “This paper describes the design of an integrated accelerator to offload computation intensive protocol-processing tasks. The accelerator combines the concepts of the transport-triggered architecture with a programmable finite-state machine to deliver high instruction-level parallelism, efficient multiway branching and flexibility. The flexibility is key to adapt to protocol changes and address new applications.” Learn more at: http://hoti.org
    • A Low-Latency Library in FPGA Hardware for High-Frequency Trading

      Posted: 2012-08-24 15:02:43 UTC
      In this video, John Lockwood from Alto-Logic presents: A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). Recorded at the Hot Interconnects 2012 conference in Santa Clara. “Current High-Frequency Trading (HFT) platforms are typically implemented in software on computers with high-performance network adapters. The high and unpredictable latency of these systems has led the trading world to explore alternative “hybrid” architectures with hardware acceleration. In this paper, we describe how FPGAs are being used in electronic trading to approach the goal of zero latency. We present an FPGA IP library which implements networking, I/O, memory interfaces and financial protocol parsers. The library provides pre-built infrastructure which accelerates the development and verification of new financial applications. We have developed an example financial application using the IP library on a custom 1U FPGA appliance. The application sustains 10Gb/s Ethernet line rate with a fixed end-to-end latency of 1μ – up to two orders of magnitude lower than comparable software implementations.” Learn more at: http://hoti.org
    • ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification Posted: 2012-08-22 23:55:38 UTC.
    • In this video, Jeffrey Fong presents: ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification. Recorded at the Hot Interconnects 2012 conference in Santa Clara. “Packet classification is a fundamental enabling function for various applications in switches, routers and firewalls. Due to their performance and scalability limitations, current packet classification solutions are insufficient in addressing the challenges from the growing network bandwidth and the increasing number of new applications. This paper presents a scalable parallel architecture, named ParaSplit, for high-performance packet classification. We propose a rule set partitioning algorithm based on range-point conversion to reduce the overall memory requirement. We further optimize the partitioning by applying the Simulated Annealing technique. We implement the architecture on a Field Programmable Gate Array (FPGA) to achieve high throughput by exploiting the abundant parallelism in the hardware. Evaluation using real-life data sets show that ParaSplit achieves significant reduction in memory requirement, compared with the-state-of-the-art algorithms such as HyperSplit and EffiCuts. Because of the memory efficiency of ParaSplit, our FPGA design can support in the on-chip memory multiple engines, each of which contains up to 10K complex rules. As a result, the architecture with multiple ParaSplit engines in parallel can achieve up to Terabit per second throughput for large and complex rule sets on a single FPGA device.” Learn more at: http://hoti.org

    The Following Videos Appeared on inside-Cloud.com

    • Video: How SDNs Will Tame Networks
    • www.youtube.com/watch?v=8Q9lSkGyQ84 In this video, Nick McKeown from Stanford presents: How SDNs Will Tame Networks. Networks are notoriously hard to debug. Today, we only have a rudimentary set of tools available, such as ping, traceroute, tcpdump, and netflow. These tools try to reconstruct the distributed state of the network in an ad-hoc fashion, while the state [...]
    • Video: Electronic-Photonic Integration within Switches and Routers

      www.youtube.com/watch?v=wJvvHD7PTWU In this video, Michael R. Watts from MIT presents: Electronic-Photonic Integration within Switches and Routers. We review recent successes in silicon photonics and how the new capabilities afforded by silicon photonics will impact future Ethernet, Infiniband, and ultimately optical domain switches and routers. Specifically, we consider the impact silicon photonics can have on the [...]
    • Video: The OpenOnload User-level Network Stack

      www.youtube.com/watch?v=-J6d3fIf5mo In this video, Dave Parry from SolarFlare presents: The OpenOnload User-level Network Stack. This talk presents the OpenOnload architecture for user-level networking, which is rapidly becoming the de-facto standard for user-space protocol processing of TCP and UDP particularly in latency sensitive applications for the financial markets. We describe our solutions to the challenges outlined [...]
    • Video: The Future Of Network Technology – What is Old, is New Again

      www.youtube.com/watch?v=RWAahWzX2UU In this video, the Hot Interconnects 2012 conference kicks off with a keynote by John Roese, VP and General Manager of Futurewei, Huawei’s North American R&D organization. Cloud, SDN, Big data, Mobility, BYOD, etc… We are currently in an industry filled with major new technologies and architectures and each of them looks like a [...]


    Read the entire post …

    Video: A Low-Latency Library in FPGA Hardware for High-Frequency Trading

    Search Results for: fpga

    In this video, John Lockwood from Algo-Logic presents: A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). Recorded at the Hot Interconnects 2012 conference in Santa Clara.

    Current High-Frequency Trading (HFT) platforms are typically implemented in software on computers with high-performance network adapters. The high and unpredictable latency of these systems has led the trading world to explore alternative “hybrid” architectures with hardware acceleration. In this paper, we describe how FPGAs are being used in electronic trading to approach the goal of zero latency. We present an FPGA IP library which implements networking, I/O, memory interfaces and financial protocol parsers. The library provides pre-built infrastructure which accelerates the development and verification of new financial applications. We have developed an example financial application using the IP library on a custom 1U FPGA appliance. The application sustains 10Gb/s Ethernet line rate with a fixed end-to-end latency of 1μ – up to two orders of magnitude lower than comparable software implementations.”

    Download the slides (PDF).


    Read the entire post …

    Posted in Events, Hot Interconnects, HPC, HPC Hardware, Network, Video | Leave a comment

    ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification

    Search Results for: fpga

    In this video, Jeffrey Fong presents: ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification.

    Packet classification is a fundamental enabling function for various applications in switches, routers and firewalls. Due to their performance and scalability limitations, current packet classification solutions are insufficient in addressing the challenges from the growing network bandwidth and the increasing number of new applications. This paper presents a scalable parallel architecture, named ParaSplit, for high-performance packet classification. We propose a rule set partitioning algorithm based on range-point conversion to reduce the overall memory requirement. We further optimize the partitioning by applying the Simulated Annealing technique. We implement the architecture on a Field Programmable Gate Array (FPGA) to achieve high throughput by exploiting the abundant parallelism in the hardware.”

    Recorded at the Hot Interconnects 2012 conference in Santa Clara. Download the slides (PDF).


    Read the entire post …

    Posted in Events, Hot Interconnects, HPC, HPC Hardware, Network, Video | Leave a comment

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