Search Results for: “hype”

ScaleMP Using RAM plus vSMP to Boost Server Performance

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ScaleMP uses is vSMP aggregation hypervisor and cheap skinny nodes to boost main memory

Over at The Register, Timothy Prickett-Morgan writes that ScaleMP has cooked up some new ways to build big memory machines for less money.

In the example above, the workload in question only needs a four-socket Xeon E5-4600 or Xeon E7-4800 in terms of the processing capacity, but the 48 to 64 memory sticks in this box do not offer enough main memory capacity, and moreover, the fat memory needed to build up terabytes of memory space are very expensive. So instead of buying an eight-socket box to get more memory slots, you get the four-socket box and put in the faster Xeon or Opteron processors you can afford. Then you buy a bunch of skinny server nodes with 24 memory sticks each, and you turn off the cores and leave on the memory controllers and memory in the boxes as well as the InfiniBand ports, and now the FDR links are effectively a backplane for an SMP based on the vSMP hypervisor.

If this sounds enticing, the good news is that there will soon be an easy way to kick the tires and give it a try. Morgan also writes that ScaleMP plans to roll out a variant of vSMP Foundation called Memory Expansion Free. As a free download without support, Memory Expansion Free will have one compute node and up to a total of eight nodes in a cluster and is also limited to four sockets of processing in a machine and 1TB of aggregate main memory across the server nodes in the cluster.

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How IBM’s Potential Sale of its x86 Business Could Impact the HPC Market

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Over at The Register, Timothy Prickett Morgan writes that IBM may be selling its x86 server business to Lenovo.

If IBM actually has a plan that gets it into hyperscale data centers – possibly with ARM, Atom, and Power microservers, possibly deploying some of the Power AS and torus interconnect in the BlueGene/Q supercomputers – and if IBM will use at least some of the funds from a Lenovo deal to do the engineering to make modern servers, then dumping System x might be worth it. It would be quite interesting, in fact, to see IBM become an ARM licensee and offer both ARM and Power alternatives. But IBM is probably more inclined to think it can push Power into an x86-dominated data center, and do so despite all the hype and real engineering with ARM processors for servers.

As to what such a deal means to the HPC market, I think this vendor chart from the November 2012 TOP500 is very telling. IBM clearly has the largest share of the TOP500, and even though this represents a mix of Blue Gene, Power, and x86 systems, a sale to Lenovo could result in a Chinese multinational becoming the number one vendor on the TOP500.

Ouch!

As you’ll recall, IBM sold off its unprofitable PC business to Lenovo back in December 2004. According to reports, IBM will not be selling its new FlexSystems in this deal.

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Altair HyperWorks 12 Release Focuses on Simulation-Driven Design

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Today Altair announced the release of the HyperWorks 12.0 computer-aided engineering platform. With new functionalities and end-user productivity advancements in product optimization, Version 12 has already received accolades from customer beta users.

The new 3D capability creates a fully-immersive environment that improves our ability to support conceptual design and analysis efforts,” said Jonathan Gabrys, Technical Fellow of The Boeing Company. “Specifically, being able to interrogate complex analysis results, such as stress fields or deflections, using 3D visualization provides an enhanced level of understanding.”

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Silicon Mechanics on Board with Nvidia K20 GPUs

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This week Silicon Mechanics announced that the company is offering the new NVIDIA Tesla K20 GPUs in its hybrid architecture server product line. Designed for high throughput of both dual- and single-precision workloads, Kepler GPUs are ideal for climate and weather modeling, computational fluid dynamics, computer-aided engineering, computational physics, biochemistry simulations, and computational finance.

With more than one teraflop peak double-precision performance, this GPU Accelerator is ideal for the most aggressive high-performance computing workloads,” said Sumit Gupta, senior director of Tesla business at NVIDIA. “Since it is not limited to single-precision applications, it is also a well-rounded offering that can be used by more people for more tasks.”

The K20 GPU Accelerator features a single GK110 Kepler GPU that includes the innovative Dynamic Parallelism and Hyper-Q features, which boost performance and power efficiency, and deliver record application speeds. Read the Full Story.

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Stanford Researchers Conduct First-ever Million-core CFD Run on Sequoia Super

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Andrew Myers writes that Stanford researchers using the Sequoia IBM Bluegene/Q system at LLNL have set a new record, harnessing a million compute cores to model supersonic jet noise.

These runs represent at least an order-of-magnitude increase in computational power over the largest simulations performed at the Center for Turbulence Research previously,” said Joseph Nichols, a research associate in the center. “The implications for predictive science are mind-boggling.” Sequoia once topped list of the world’s most powerful supercomputers, boasting 1,572,864 compute cores and 1.6 petabytes of memory connected by a high-speed five-dimensional torus interconnect. Because of Sequoia’s impressive numbers of cores, Nichols was able to show for the first time that million-core fluid dynamics simulations are possible—and also to contribute to research aimed at designing quieter aircraft engines.”

In addition to jet noise simulations, Stanford researchers in the DoE-sponsored Predictive Science Academic Alliance Program are using the CharLES code to investigate advanced-concept scramjet propulsion systems used in hypersonic flight and to simulate the turbulent flow over an entire airplane wing. Read the Full Story.

In related news, the HPC Advisory Council will host the Stanford HPC Conference on Feb. 7-8, 2013.

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Henry Newman’s Top Ten Storage Predictions for 2013

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Over at Enterprise Storage Forum, Henry Newman from Instrumental is out with his Ten Storage Predictions for 2012, and his last one is more of plea for reason.

The industry really needs more than POSIX (open/fopen, read/fread,write/fwrite) and more than simple REST put/get interfaces for data in the future. Neither has the richness to address the myriad of polices that are needed in our future world. I predict that there will finally be some honest discussion about this amongst the customers that need it and the vendors that could create it. Maybe this should be my request to Santa. I have tried to encourage this discussion for years and I have gotten no traction.

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Supermicro Debuts High Frequency Trading Systems

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Clipped from http://www.terrapinn.com/conference/high-frequency-trading-world-new-york/index.stm

Over at Datacenter Knowledge, John Rath writes that Supermicro launched new 2U and 4U/Tower platforms that maximize processing power and precisely tune hardware and firmware to provide lower latency than previous models, while still maintaining high reliability. The company debuted the systems at the High Frequency Trading World event this week in New York.

Advanced trading firms looking to reduce latency and maximize transaction flow can gain an advantage with the extreme processing power and enterprise-class server optimizations designed into Supermicro’s Hyper-Speed systems,” said Wally Liaw, Vice President of Sales, International at Supermicro. “Our latest HFT-optimized platforms boost performance of the fastest rated x86 dual processors with board-level control and circuitry enhancements and custom tailored cooling systems for the highest sustained performance. With mission critical transactions on the line, Supermicro Hyper-Speed systems ensure peak performance with maximum reliability for the most demanding computational finance applications.”

The new servers are optimized for high frequency trading and feautre premium pre-installed CPUs and memory, with storage and I/O components that are validated with a rigorous burn-in process to ensure maximum performance and reliability on deployment. Read the Full Story.


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Demo: Altair RADIOSS Finite Element Analysis on Intel Xeon Phi at SC12

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In this video from SC12, Eric Lequiniou, Director of High Performance Computing at Altair demonstrates a port of RADIOSS to the new Intel Xeon Phi that uses both explicit and implicit solvers.

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Netlist Demonstrates Superiority of HyperCloud Memory at SC12

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Memory speed is often cited as a bottleneck in modern HPC systems. At SC12, Netlist demonstrated a comprehensive performance benchmark of its HyperCloud (HCDIMM) that showed a 39% greater server throughput compared to an identical system equipped with LRDIMMs.

As companies today increasingly process and capitalize on big data, there’s an increasing need for more memory in servers. However, memory performance in these servers is not keeping pace with processor technology, creating a high density memory cliff,” said C.K. Hong, CEO of Netlist. “HyperCloud breaks this bottleneck and allows servers to operate at their peak potential. By doing so, HyperCloud increases performances of applications in such key areas as securities trading, analytics, virtualization, and simulation.”

HyperCloud is shipping in volume with the world’s top three selling servers from IBM and HP, and is implemented across a number of high-performance computing applications in industries such as electronic design automation, financial services, oil & gas, aerospace and automotive. Read the Full Story.

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Altair Speeds RADIOSS at SC12 Using Intel Xeon Phi

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In this video from SC12, James Reinders and Paresh Pattani from Intel discuss how the new Intel Xeon Phi is already powering engineering applications like RADIOSS. Altair was able to port both the explicit and implicit versions of the RADIOSS code in short order.

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SGI Big Brain Supers have Intel and Nvidia Inside

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Over at The Register, Timothy Prickett Morgan writes that SGI has reworked its high-end UV 2000 shared memory supers and its Rackable hyperscale machines to include the latest Intel Xeon Phi and
Nvidia Kepler coprocessors.

Initially, SGI is allowing for up to 32 of these accelerator blades to be added to a UV 2000 system. In an all-Xeon setup, the UV 2000 can support a maximum of 256 single-node processors for a total of 2,048 Xeon E5 cores and 64TB of memory. What would be even more interesting is for SGI to push the NUMALink 6 to its full 512-socket theoretical limit and offer a 256 CPU by 256 accelerator configuration.

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Interview: Numascale Aggregates Big Memory with Commodity Servers

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Does your application need Big Memory to run efficiently? Numascale has been making waves of late with their rather clever hardware-based server aggregation platform. To learn more, I caught up with their VP of Business Development, Einar Rustad.

insideHPC: How does NumaConnect enable large shared-memory systems to be built from commodity servers?

Einar Rustad: We have developed an ASIC with all the logic including distributed switching for 1-, 2- and 3-D Torus topologies. The chip is mounted on a PCB for plugging into HTX. For boxes that lack HTX connector we have a solution which picks up the HyperTransport signal from a CPU socket.

insideHPC: How is cache-coherency maintained amongst so many nodes?

Einar Rustad: This is done with 64 byte cache line granularity (same as the processor caches) through a directory based coherency protocol.
We use DRAM for storing tag information and another for storing remote cache lines. We call this “Remote Cache”, but it is local to each node and mounted on our PCB. One such PCB is used for each motherboard. This is then an L4 cache and the size is configurable from 2 to 8 GBytes per node.

insideHPC: What is your largest deployment to date and how well does it perform?

Einar Rustad: The largest that has been tested by a customer is a 32-node system with 384 cores and 1 TByte main memory. The test was very successful with the system showing linear scalability versus a cluster solution that had negative scaling beyond a single node. The application was doing reverse time migration (RTM) seismic data processing.

The largest to be installed these days is a 72-node system based on the IBM x3755 with a total of 1728 cores an 4.6 TBytes main memory.

insideHPC: How does the Numascale hardware performance compare to software-based server aggregation solutions?

Einar Rustad: We do not have any relevant performance data from software-based solutions since all the benchmarks we have seen from those are running applications that can fit the data set in the memory of a single node. Since these solutions necessarily have to be based on the minimum 4k page granularity rather than 64 byte cache lines, we can hardly believe that they will perform very well on codes that have a reasonably random access pattern in a memory space that exceeds the memory of a single node. In fact we have had customers with such systems ask us to run a simple program that touch different pages around the whole memory space and that were really impressed when this was done in a short blink of a second, whereas this basically brings a software based system to a halt.

insideHPC: How does the ability to run extremely large problems in-memory change the way researchers do science?

Einar Rustad: We believe that hey can be much more productive since they can keep entire data sets in memory without having to decompose them. Especially graph processing will be much more efficient with 1-2 microsecond access to any record within up to a 256TByte memory space. The programming model for shared memory is also much easier than the explicit massage passing with less code (approximately 50%) and correspondingly fewer bugs. This will increase programmers productivity and also expand the community of programmers that can write software for such systems since the programming model is exactly the same as for their desktop or even laptop. In fact, one interesting comment from the guy that tested the seismic code was: The system is so easy to use; it works just like my laptop except that it is much bigger and more powerful!

insideHPC: How does the price of a Numascale cluster made from commodity servers compare to a comparable large-memory SGI UV system?

Einar Rustad: From what we have seen the difference is about a factor of ten.

You can check out Numascale at SC12 booth #3218.

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Remote Visualization of Big Data with Altair Display Manager

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Today at SC12, Altair (booth #3015) unveiled Display Manager, a new portal for remote visualization of extremely large models developed from Big Data resources.

Remote visualization is a key Big Data technology, allowing huge datasets to be manipulated from thin clients,” said Bill Nitzberg, chief technology officer for PBS Works at Altair. “Display Manager leverages Altair’s deep knowhow in modeling and visualization from our globally acclaimed HyperWorks suite to deliver an amazing remote visualization experience directly from the Web browser, without the need to install any apps on the desktop.”

Display Manager, which will become generally available in the near future, enables users to run graphics-intensive applications on their cluster while visualizing those applications on their desktop.
Because applications run directly from the data center, users can take advantage of shared, powerful, GPU-enabled hardware in the data center – and use their Web browser to view, edit, interact with and control the graphical apps remotely. Read the Full Story.

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Hengeveld: SC12 – A Path to Discovery, Changing Course through Outer Space

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In this special guest feature, Intel’s John Hengeveld looks ahead to the SC12 conference.

The HPC industry is driving fast down a familiar road. SC12 represents a sharp turn for the industry. We are going to see inflection point in Salt Lake City in a few dimensions. I am beyond excited by the dynamics of this industry today.

Let me share what I am looking for:

In the past year, Big Data has emerged as a premier investment in business and academia. The use of HPC in the analysis of Big Data and how Big Data technology is going to evolve beyond Hadoop is going to be a major topic of discussion in the sessions and in the industry. How will storage change? How will compute change? How will this increased data bandwidth requirement be reflected in emerging interconnect models? I expect to find answers to these questions at SC12.

The top 10 supercomputers will be very interesting this time around. There has been relatively little change in the past 2 lists in the top10. It will be fascinating to see if there is a lot of change. How high up will the Titan monster go? What efficiency will it achieve? What other new systems will there be in the top 10? One very well informed person said to me in Hamburg “This top500 list is the last gasp of the dying blue gene architecture…” Is he right? Will BlueGene resurge? Or will hybrid architectures begin to retake a leadership role?

In the past year, there has emerged two competing groups are developing solutions for programming highly parallel compute devices. NVidia’s OpenACC has split off an approach to address GPU Computing and is trying to establish a competing standard to OpenMP. OpenMP last week announced its draft approach for targeting directives that support CPU, GPU and highly parallel CPU’s like Intel® Xeon Phi™ coprocessors. Very serious people are supporting each approach; Intel is supporting OpenMP 4.0, of course. Some people are trying to support both. It will be interesting to see how heavily NVidia hawks their approach.

What will the industry say about Intel® Xeon Phi products? In June, Intel announced this branding for products for the now famous Intel® Many Integrated Core (MIC) architecture. Is the industry moving these products into reality? What is the time table? What are the products? How many people are taking this architecture approach seriously?

We have seen some announcements about SGI and Cray new architectures leading up to SC12. What will we hear more about them? How will the major OEMs respond? Cray just went live with their press release on Cascade (X30). Looking forward to event that announces it.. and of course the Cray Party.

What is happening in the storage world in support of HPC and Big Data? What about any new technologies to help improve IO bandwidth?
Are there any new approaches for the missing middle? – Lots of hype so far – where are the proof points and examples?

The industry is going a thousand miles an hour towards exascale and deep Petascale. But it’s a bit cloudy and just how the path will change ahead is unclear. In about a week I think we’ll know where we’re going.

Editor’s note: insideHPC would like to send out condolences to John Hengeveld and his family. His wife Jen’s brother died in a tragic car accident this week. If you see her with John at SC12 next week, he says to be sure to give her a hug.

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Nvidia to Host Free Developer Sessions at SC12

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Nvidia will be hosting a set of free developer sessions at SC12 in Salt Lake City.

  • Getting Started with CUDA on Monday, November 12, 2pm – 3:30pm.
    • Massively parallel NVIDIA GPUs provide the bulk of the computing power behind many of the World’s top supercomputers. This talk will start with the basic architecture of the GPU and introduce the CUDA parallel computing platform. The basic principles of massively parallel computing will be introduced using simple source code examples of CUDA C and C++. Learn about the latest software and tools, from where to download and install, to how to get started writing your own parallel code in Linux, Mac or Windows environments. Register now.

 

  • Accelerating Your Applications with the Kepler Architecture on Monday, November 12, 4pm – 6pm.
    • The recently introduced Kepler architecture offers a wealth of new features to assist programmers developing applications on the GPU and help them achieve unprecedented performance. While many of these features are leveraged transparently by the NVCC compiler and the CUDA software tool chain, programmers can support these tools by targeting the Kepler architecture with their software design. The goal of this presentation is to provide CUDA developers with an understanding of the key concepts of the Kepler architecture and demonstrate how they can be used in real world applications. After a review of the Kepler architecture and a brief introduction of general GPU optimization strategies, we will present an in-depth look at Kepler features targeting both coarse-grain and fine-grain parallelism, including dynamic parallelism, Hyper-Q, warp shuffle and more. This will provide CUDA developers with the necessary background to make the optimal design choices for Kepler. Register now.


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