insideHPC » Computing Research

Slidecast: GPU Computing and the Road to Extreme-Scale Parallel Systems

Rich Brueckner — Fri, 03 Feb 2012 13:00:40 +0000

www.youtube.com/watch?v=4IH5X12knqU

In this slidecast, Nvidia’s Steve Keckler describes the evolutionary path of GPU computing and where it’s heading on the road to Exascale computing. Keckler is part of the team working on the company’s Echelon research project, which is looking into technologies that will eventually enable an Exaflop supercomputer to operate at under 20 Megawatts.

Nvidia’s Echelon extreme-scale computing project is partly funded by DARPA under the Ubiquitous High Performance Computing (UHPC) program. The other UHPC program teams include the X-Caliber team led by Sandia National Laboratories, the Intel UHPC Runnemede team, and the Angstrom team led by MIT.

The Ubiquitous High Performance Computing (UHPC) program seeks to develop the architectures and technologies that will provide the underpinnings, framework and approaches for the resolution of power consumption, cyber resiliency, and productivity problems. The UHPC program aims to develop computer systems, from embedded to cabinet level, which have extremely high energy efficiency and are dependable and easily programmable. These systems will have dramatically reduced power consumption while delivering a thousand-fold increase in processing capabilities. Dependability technologies developed under the UHPC program will provide adaptable and hardened cyber resilient computer systems. Productivity will be significantly improved by developing scalable, highly programmable computer systems that will not require significant system expertise for the development of high performance applications.

Download the MP3 * Subscribe on iTunes * If Dropbox is blocked, download from this Google page.

Video: EPFL Scientists Develop 3D Chips

Rich Brueckner — Thu, 02 Feb 2012 13:00:11 +0000

www.youtube.com/watch?v=x3z-O8rrQis

EPFL scientists have developed a new generation of 3D computer chips that stacked vertically rather than placed side by side. The technology may someday enable faster, higher bandwidth processing.

EPFL scientist are among the leaders in the race to develop an industry-ready prototype of a 3D chip as well as a high-performance and reliable manufacturing method. The chip is composed of three or more processors that are stacked vertically and connected together—resulting in increased speed and multitasking, more memory and calculating power, better functionality and wireless connectivity.

Read the Full Story.

PRACE Research Initiative Welcomes Denmark, Israel, and Slovenia

Ralph — Tue, 31 Jan 2012 19:39:01 +0000

The European PRACE Research Infrastructure has announced three new members: Denmark, Israel and Slovenia. Now 24 member countries strong, PRACE is a non-profit organization with a mission to: “enable high impact European scientific discovery and engineering research and development across all disciplines to enhance European competitiveness for the benefit of society.”

This clearly shows the high-level of interest in High-performance Computing (HPC) by so many European Member States and Associated States to the Framework Programme for Research and Technological Development in Europe. PRACE aims to be the living proof of the successful exploitation of HPC as a tool for innovation in Research and Industry in Europe”, said Dr. Maria Ramalho, Chair of the Board of Directors of the PRACE Research Infrastructure.

Read the Full Story.

Beyond Binary: Phase-change Materials Could Fix Memory Crunch

Ralph — Mon, 30 Jan 2012 19:00:02 +0000

Duncan Graham-Rowe from New Scientist writes that new Phase Change Memory (PCM) materials that can hold multiple states at once could take digital information beyond just 1s and 0s. The technology, which is still in the laboratory at places like IBM’s Zurich Research Laboratory in Switzerland, would enable multiple bits to be stored in a single cell.

The idea is simple: why use a single memory cell to store two binary states when it could hold many more? The technology relies upon phase change materials (PCMs) that can hold information by switching between an amorphous state and a crystalline one. PCM memory can write and retrieve data 100 times faster than Flash memory, which is used in many consumer gadgets and computers. It is also extremely durable and can be reused at least 10 million times; Flash can cope with just 3000 uses.

PCM technology is still a ways off, according to David Wright at the University of Exeter in the UK. Differentiating between distinct states requires highly sensitive and expensive equipment, which isn’t currently practical in a chip, he said.

Read the Full Story.

DARPA Shoots for Power Efficiency Revolution with PERFECT Workshop

Rich Brueckner — Mon, 30 Jan 2012 16:23:06 +0000

Clipped from: www.darpa.mil (share this clip)

One of the toughest hurdles on the road to Exascale is processing power efficiency. This week DARPA announced a new initiative called the Power Efficiency Revolution for Embedded Computing Technologies, or PERFECT. The initiative will kick off with a Proposer’s Day Workshop in Arlington, Virginia on February 15.

PERFECT aims to achieve the 75 GFLOPS/w goal by taking novel approaches to processing power efficiency. These approaches include near threshold voltage operation and massive heterogeneous processing concurrency, combined with techniques to effectively use the resulting concurrency and tolerate the resulting increased rate of soft errors. The program seeks to leverage and incorporate anticipated industry fabrication geometry advances to 7 nanometers. PERFECT does not plan to build hardware, rather it seeks to develop a simulation capability to measure and demonstrate progress. It plans to specifically address embedded systems processing power efficiencies and performance, and is not concerned with developments that focus on exascale processing issues.

Read the Full Story.

New Whitepaper: Boost RAM Bandwidth by 20% with a Single Command

Rich Brueckner — Fri, 27 Jan 2012 13:15:39 +0000

Colfax International has published a new whitepaper by Stanford’s Andrey Vladimirov entitled: Terabyte RAM Servers: Memory Bandwidth Benchmark and How to Boost RAM Bandwidth by 20% with a Single Command.

Colfax International produces servers capable of supporting up to 1 TB of RAM and up to 4 Intel Xeon CPUs. This paper reports the memory bandwidth benchmark of these servers obtained using the STREAM code. Our benchmark includes comprehensive statistical data: the mean, standard deviation, extrema and the distribution of bandwidth measurements. The distribution of measurements reveals several modes of RAM performance, including an above-average bandwidth mode. By default, the mode realized by any given benchmark depends on an unpredictable runtime pattern of thread and memory binding to the physical cores. The paper shows how to optimize memory traffic for bandwidth and consistently achieve the fastest mode. This is done by controlling the code’s thread affinity, and results in a bandwidth increase around 20% over the average unoptimized performance.

Download the whitepaper (PDF).

University of Manchester to Head Up Algorithm Network

Rich Brueckner — Thu, 26 Jan 2012 19:20:53 +0000

This week the University of Manchester announced it is heading up a large interdisciplinary network of institutions focused on numerical algorithms and HPC. Funded by the Engineering and Physical Sciences Research Council (EPSRC), the network will develop short courses and workshops for training undergrad and postdoctoral researchers.

This is an exciting opportunity to bring together numerical analysis and computer science researchers with scientists and engineers who use numerical software for high performance computing,” said Professor Nick Higham. “The major challenges are to develop new numerical algorithms for analysing increasingly large and complicated mathematical models and to build associated software that exploits multicore processors, which are often used with graphics processing units or field-programmable gate arrays as accelerators.”

The network comprises0 The University of Manchester, NAG Ltd, Centre for Numerical Algorithms and Intelligent Software (NAIS), The University of Oxford, Science and Technology Facilities Council (STFC) and University College London (UCL).

Read the Full Story.

Nanomappers – Harvard and PSC Chart Brain Connections

Ralph — Tue, 24 Jan 2012 21:00:09 +0000

In a move towards developing a complete wiring diagram of the brain, Harvard and the Pittsburgh Supercomputer Center have developed study approach that makes it possible to identify the function of individual brain cells and map the connections between them.

We’ve just begun to scratch the surface,” says Clay Reid, professor of neurobiology at the Harvard Medical School and Center for Brain Science, who led the project, ”but we’re moving toward a complete physiology and anatomy of cortical circuits.”

To create the map, Reid and his colleagues developed an advanced TMR microscope that captured high resolution photographs of extremely thing slices of a mouse brain. Hundred of Terabytes of image files were then transfered to PSC for archival and processing.

What we’ve done,” says Wetzel, referring to the paper in Nature, “is about 1/80th of the target volume for our next step, a cubic millimeter, large enough to encompass a circuit.” In preparation for the larger volume, he and Hood have begun upscaling their storage and processing capabilities to handle as much as 100 terabytes, and expect to be prepared to handle data transmission at the scale of petabytes (1000 terabytes) in two to three years.

Read the Full Story.

Researchers Discover Faster than Fast Fourier Transform

Ralph — Sun, 22 Jan 2012 17:59:21 +0000

MIT researchers have discovered a way to increase the speed of Fourier Transform, a method for representing an irregular signal and one of the most fundamental concepts in the information sciences.

At the Association for Computing Machinery’s Symposium on Discrete Algorithms (SODA) this week, a group of MIT researchers will present a new algorithm that, in a large range of practically important cases, improves on the fast Fourier transform. Under some circumstances, the improvement can be dramatic — a tenfold increase in speed. The new algorithm could be particularly useful for image compression, enabling, say, smartphones to wirelessly transmit large video files without draining their batteries or consuming their monthly bandwidth allotments.

Read the Full Story.

Video: 6-Minute Primer on Memristors

Rich Brueckner — Fri, 20 Jan 2012 13:00:44 +0000

In this video, R. Stanley Williams provides a quick-and-dirty guide to Memristors – the fourth fundamental circuit element. In October 2011, HP projected the commercial availability of memristor technology within 18 months, as a replacement for Flash, SSD, DRAM and SRAM.

Video: Immersive Cooling from Green Revolution Computing

Rich Brueckner — Wed, 18 Jan 2012 15:37:04 +0000

www.youtube.com/watch?v=JkuCFA1Vtio

In this video from TACC, Christiaan Best from Green Revolution Computing describes the company’s immersive cooling technology and how he got the idea.

Christiaan Best was sitting in a field when the initial idea for his company took root. A friend was telling Best about the cooling systems being installed at the North American Aerospace Defense Command (NORAD), where he worked, and the plans were so inefficient, so counterintuitive, that it started Best on a search for alternatives. Some months later, enjoying a meal with one of his friends at Magnolia Café in Austin, Texas, he had a eureka moment and sketched an idea for a new data center cooling system on the back of a napkin. The idea involved building a rack that could hold densely packed computer servers in a circulating bath of liquid mineral oil.

Marc Hamilton on HPC Design Challenges

Rich Brueckner — Tue, 17 Jan 2012 12:30:34 +0000

HP’s Marc Hamilton came away from a recent meeting on future HPC Design Challenges with some interesting thoughts on power, cooling, and IO.

Flash roadmaps are well understood and seeing evolutionary improvements. However, the looming mainstream introduction of PCIeGen3 server interconnects and new PCIeGen3 flash controllers offers interesting possibilities. To take advantage of the storage bandwidth possible with PCIeGen3 will require rethinking the software interface. Strip away legacy storage protocols (FC, SCSI, SAS, etc.) and even perhaps the file system and you now have real possibilities. Longer term, today’s flash technology will give way to fundamental new memory technologies, such as HP’s memristor which promise to provide not only new levels of performance but significantly lower power usage.

Read the Full Story.

Video: Building Memory One Atom at a Time

Rich Brueckner — Thu, 12 Jan 2012 20:17:12 +0000

www.youtube.com/watch?v=hpKMShooDBo

In this video from IBM research labs, Almaden physicist Andreas Heinrich explains how he and his teammates started with 1 atom and a scanning tunneling microscope and eventually succeeded in storing one bit of magnetic information reliably in 12 atoms.

Andreas Heinrich, the project lead for IBMs efforts, explained in an interview that this tech may never be realized in part because it requires an entirely new type of manufacturing equipment to be built. However, IBM is learning how to manipulate atoms for storing bits and identified a new type of magnetism that could one day be used. Unlike the type of magnetism that keeps your magnets stuck to your fridge, IBM is looking at the reverse of those properties to make this highly dense type of memory.

Read the Full Story by GigaStacey.

Goh’s 2012 Predictions: Personal Genomics this Year

Ralph — Wed, 04 Jan 2012 19:34:41 +0000

SGI CTO Eng Lim Goh has posted Ten 2012 HPC predictions in Bio-IT World. At the top of the list is the fruition of personal genomics.

Technical computing will bring truly personalized medicine: The cost of personalized genome sequencing has come down to be on par with the cost of a standard MRI, and time-to-insight for researchers is accelerating. In the next 12 months we’ll see drugs designed, produced, and administered according to a patient’s specific genomic pattern.

Read the Full Story.

EMC Collaborating with Los Alamos to Advance HPC

Rich Brueckner — Wed, 28 Dec 2011 12:33:14 +0000

This week Los Alamos National Laboratory announced the signing of a new Umbrella CRADA (Cooperative Research and Development Agreement) with EMC Corporation. Under the agreemnt, LANL and EMC will collaborate over the next five years to enhance, design, build, test, and deploy new technologies including HPC, data storage, cyber security, data sharing and mobility, cloud computing, large-scale analytics, and materials science.

We are thrilled to work with some of the nation’s greatest scientists at LANL, where the first petascale supercomputer was deployed, to collaboratively innovate in an effort to help maintain our nations’ leadership in extreme computing, on the road to exascale,” said Dr. Percy Tzelnic, senior vice president and EMC Fellow.

Read the Full Story.

OSC Powers Better Turbine Simulations

Ralph — Wed, 21 Dec 2011 13:17:11 +0000

Turbines power our world–pumps, fans, compressors,and other machines that transfer energy between a rotor and a fluid. To help make better designs, engineers must understand the physics of very complex air-flow fields produced within multiple stages of constantly rotating rotors and stators.

Enter the research team at the Ohio Supercomputer Center lead by Dr. Jen-Ping Chen. The team is working to improve the CFD software that engineers use to simulate and evaluate the operation of turbomachinery. Chen was the chief architect of that type of computer code, appropriately named TURBO, which he developed earlier for NASA.

The world is demanding increasingly cleaner, more efficient and reliable power systems,” noted Ashok Krishnamurthy, interim co-executive director of OSC. “Therefore, it is essential that experts like Dr. Chen find innovative ways to improve the tools the engineers need to accomplish that goal, and we at OSC are proud to be able to provide the computational resources that make that effort successful.”

Read the Full Story.

Korean Tachyon II Supercomputer Runs Largest Simulation of the Universe

Rich Brueckner — Mon, 19 Dec 2011 15:42:13 +0000

A Korean supercomputer called Tachyon II has completed the largest ever simulation of the universe. Ranked at #26 on the TOP500, Tachyon II took over 20 days to run the job on 26,232 processing cores. The purpose of the study – called Horizon Run 3 – was to run the birth and evolution of the universe to see if it ends up with the same properties as the one we see around us, including galactic clusters and super-clusters.

This is a mind-boggling, ambitious project,” said Dr. Heather Couper. “It will shed light on the past and future of our universe – and give us insights into the mysterious dark matter that makes up so much of our cosmos, and the unknown dark energy that drives it.”

Read the Full Story.

Video: (Astro)-Physical GPU Supercomputing in China and Elsewhere – Galaxies, Black Holes, Gravitational Waves

Rich Brueckner — Fri, 16 Dec 2011 00:38:20 +0000

www.youtube.com/watch?v=6OxhyGYJtdo

In this video, Rainer Spurzem, a visiting professor of Chinese Academy of Sciences in Beijing presents: (Astro)-Physical GPU Supercomputing in China and elsewhere - galaxies, black holes, gravitational waves.

New powerful supercomputers have been built using graphical processing units (GPU) for general purpose computing. China has obtained top ranks in the list of the fastest supercomputers in the world with such systems. The research of Chinese Academy of Sciences and National Astronomical Observatory in Beijing with such GPU clusters will be reviewed, present and future applications in computer simulation and data processing discussed. We present particle- and mesh-based algorithms for astrophysics using hundreds to thousands of GPUs for one single application run in a parallel message passing environment, some with detailed timing models. Future perspectives for GPU and FPGA accelerated computing will be discussed and international collaboration in the ICCS (International Center for Computational Science). GPU and other ‘green’ supercomputing hardware is a stepping stone on the path to reach Exascale supercomputing. An application to astrophysical Computer Simulations of Dense Star Clusters in Galactic Nuclei with Supermassive Black Holes is presented. We use large high-accuracy direct N-body simulations with Hermite scheme and block-time steps, parallelised across a large number of nodes on the large scale and across many GPU thread processors on each node on the small scale. We reach a sustained performance of more than 350 Tflop/s for a science run on 1600 Fermi C2050 GPUs; a performance model is presented and studies for the largest GPU clusters in China with up to Petaflop/s performance and 7000 Fermi GPU cards. Our simulation proceeds to the complete relativistic merger of the black holes, including Post-Newtonian corrections to gravitational forces and the relevance of the results for the cosmological background of gravitational radiation is briefly touched. We discuss the relevance of this for pulsar timing bands and for frequency bands of new space based gravitational wave missions in China and Europe.

Recorded at the GTC Asia Conference on Dec. 15, 2011.

Video: Petaflop Biofluidics Simulations on the TSUBAME 2.0 Supercomputer

Rich Brueckner — Thu, 15 Dec 2011 02:23:50 +0000

www.youtube.com/watch?v=5jg5wTAL-os

In this video, Simone Melchionna, a researcher at the National Research Council’s Institute for Physico-Chemical Processes, presents: Petaflop Biofluidics Simulations on the TSUBAME 2.0 Supercomputer.

We present a computational framework for multi-scale simulations of real-life biofluidic problems and applied to the simulation of blood flow through the human coronary arteries with a spatial resolution comparable with the size of red blood cells, and physiological levels of hematocrit. The simulation on Tsubame 2.0 exhibits excellent scalability up to 4000 GPUs and achieves close to 1 Petaflop aggregate performance, which demonstrates the capability to predicting the evolution of biofluidic phenomena of clinical significance. The combination of novel mathematical models, computational algorithms, hardware technology and optimization will be discussed together with an application employed to assess the vulnerability of the coronary network to atherosclerotic plaque build-up to assist clinical decision.

Recorded at the GPU Technology Conference in Beijing on Dec. 14, 2011.

Bristol Boffins Bring Qubit Computing a Tiny Step Closer

Ralph — Thu, 15 Dec 2011 01:36:54 +0000

By Richard Chirgwin • Get more from this author

Until now, quantum computing has suffered the same problem that vacuum tubes had in the 1950s: the hardware’s too damn big – a problem addressed by Bristol boffins who have put a reconfigurable two-qubit processor on a single chip.

Just creating and manipulating a pair of qubits usually needs a tabletop’s worth of equipment, explains Professor Jeremy O’Brien, director of Bristol’s Centre for Quantum Photonics.

The university’s 70 x 3 mm chip – still a very large feature size by electronics standards, but tiny in the world of quantum computing – achieves.

It can’t be regarded as a “processor”, since O’Brien also said that this chip is for conducting experiments, but it’s still a considerable advance.

The chip demonstrated by Bristol allows a variety of experiments: creating entanglement between photon pairs; manipulating photons’ states; and measuring “mixture” impacts on the photons from the outside environment.

The device comprises waveguides for the photons, and electrodes to perform quantum operations on single photons. For example, the electrodes – acting as phase shifters – can control the entangled states of two photons (as O’Brien described them, “IC qubits”), or the mixed (ie, the impact of environmental noise) state of a single photon / ICqubit.

This chip, Dr O’Brien told The Register, works in one degree of freedom – the photon’s path. This still provides very broad entangled states for experimentation: “you can think of the state as being parameterized by several continuous numbers,” O’Brian said. “We can control these parameters continuously using the phase shifters we have on-chip.”

Reconfigurability is the other key characteristic of the device, since many different experiments can be performed on one device, under software control.

The research is published in Nature Photonics.®

This article originally appeared in The Register. It appears here in its entirety as part of a cross-publishing agreement.