insideHPC » Events

Video: Titan Supercomputer Session Showcases Science on GPUs

Rich Brueckner — Fri, 25 May 2012 16:13:57 +0000

In this video from GTC 2012, Jack Wells, Director of Science at ORNL introduces a series of talks on the research that will be accelerated by the hybrid Titan supercomputer.

The whole system is an upgrade,” said Jack Wells in describing how Oak Ridge’s current Jaguar supercomputer is being transformed into Titan. ORNL is transitioning from Cray’s XT5 compute blades to their XK6 compute blades, which use hybrid chipsets comprised of AMD Opteron CPUs and NVIDIA Tesla GPUs. Application benchmarks conducted thus far have demonstrated that the XK6 is yielding performance improvements ranging from 50 percent to 230 percent compared with the XT5.

The following talks comprised the rest of the session:

Slidecast: ScaleMP Update on Server Aggregation

Rich Brueckner — Fri, 25 May 2012 11:30:28 +0000

www.youtube.com/watch?v=zkc19eExSRc

In this slidecast, Shai Fultheim from ScaleMP provides an update on the company’s virtualization software solutions for HPC. The company is preparing a big announcement at ISC’12. You can hear some of the details here or check out their booth #303 in Hamburg.

The innovative Versatile SMP (vSMP) architecture aggregates multiple x86 systems into a single virtual x86 system, delivering an industry-standard, high-end symmetric multiprocessor (SMP) computer. Using software to replace expensive custom hardware and components, ScaleMP offers a new, revolutionary computing paradigm.

Download the MP3 * Download the slides (PDF). Subscribe on iTunes * If Dropbox is blocked, download from this Google page.

ISC’12 Ramps up to 175 Exhibitors

Rich Brueckner — Wed, 23 May 2012 21:54:37 +0000

The good folks at ISC’12 are out with their latest newsletter and it looks like this year’s exhibition will be a record breaker with a total of 175 companies and research organizations from around the world. The conference runs June 17-21 in Hamburg, Germany.

Hot Topics at ISC’12:

Energy Efficient HPC Centers

Future Heterogeneous Architectures

Supercomputer Architectures for Data Intensive Applications

Alternative Processors, Architectures and Multidisciplinary Applications

Best Practices of Large-Scale Applications across Industries

Petascale Systems in the World and their Applications

Application Performance: Lessons learnt from Petascale Computing

Critical Aspects of High Performance Networking

The Realities and Challenges of HPC in the Cloud

Exascale Computing: Where we are?

Networking/Interconnect within HPC-Systems

Parallel File Systems

Computational Chemistry

HPC for Small and Medium Sized Enterprises

At insideHPC, we are proud to join the ranks of 54 first-time exhibitors at ISC’12. Look for the Red Hat and be sure to stop by and say hello.

Video: Programming Heterogeneous Many-cores Using Directives

Rich Brueckner — Wed, 23 May 2012 11:00:05 +0000

In this Part 1 of this video, Francois Bodin from CAPS presents: Programming Heterogeneous Many-cores Using Directives.

Directive-based programming is a very promising technology to deal with Many-Core. In this context, HPC users can rely on emerging standards such as OpenACC and OpenHMPP. CAPS will introduce OpenACC and HMPP directive-based programming models with companion tools (e.g. for tracing, tuning, debugging): HMPP Wizard, CULA, ArrayFire, Vampir, Paraver, DDT, CodeletFinder, etc. The speakers will provide insights on how GPU / CPU can be exploited in a unified manner and how code tuning issues can be minimized. The discussion will also cover the use of libraries which is essential when addressing Many-Core Programming. Pathscale will present its product supporting OpenHMPP programming model.

Recorded at GTC 2012 in San Jose. Download the slides (PDF).

In Part 2 of this video (starting at the 30 minute mark) Christopher Bergstrom from Pathscale presents: Pathscale Enzo. ENZO is a complete GPGPU and multi-core solution, which tightly couples the best programming models with highly optimizing code generation for Nvidia Tesla. Download the slides (PDF).

May 24 Webinar: How Do You Make Grid Engine Faster?

Rich Brueckner — Tue, 22 May 2012 19:54:26 +0000

In HPC, speed is everything. Join Univa’s Bill Bryce, VP Products for an all new webinar about how to make Grid Engine faster. You’ll learn about Univa Grid Engine 8.1 and the new features that translate into speed and productivity — and how they affect your business.

Each webinar will be less than 30 minutes, so you can get the practical information you need quickly.

Webinar Times :

Thursday, May 24: 13:00 – 13:30 (EDT / UTC/GMT -5 hours)

Thursday, June 15: 10:00- 10:30 (CEST/ UTC / GMT +1 hour)

Register now.

Video: GTC 2012 Full Keynote

Rich Brueckner — Tue, 22 May 2012 14:48:53 +0000

www.youtube.com/watch?v=gx3P6vm1luw

Last week, Nvidia CEO Jen-Hsun Huang rolled out the new Kepler GPUs at his GTC 2012 keynote. And while this video is available elsewhere in pieces, we thought it would be worthwhile to stitch it together as one streaming movie for our readers.

Note: Many of the GTC 2012 talks are now available as streaming video, and we plan to highlight some of our favorites in the coming days.

Video: GPUs Accelerate Risk Analysis for Financial Services

Rich Brueckner — Mon, 21 May 2012 16:22:25 +0000

www.youtube.com/watch?v=Pup6yVdJOcU

In this video, Pierre Spatz from Murex and Alastair Houston from Nvidia discuss how GPUs are being successfully used to run financial risk analysis at higher speeds and for less cost. Recorded at GTC 2012 in San Jose.

July HPC User Forums in London and Stuttgart

Rich Brueckner — Mon, 21 May 2012 16:14:42 +0000

At insideHPC, we are pleased to announce that we will co-sponsor two HPC User Forum meetings in Europe in July. The first meeting is at Imperial College London on July 5-6 and the second meeting is at the HLRS/University of Stuttgart on July 9-10. Registration is free and refreshments will be served.

The HPC User Forum was established in 1999 to promote the health of the global HPC industry and address issues of common concern to users. The organization has grown to 150 members. It is directed by a volunteer Steering Committee of HPC users from government, industry and academia, and is operated for the users by market analyst firm IDC.

The meetings will include presentations on Big Data, Blue Waters, regional supercomputing, and more. Read the Full Story.

Student Cluster Competition Comes to ISC’12

Rich Brueckner — Sun, 20 May 2012 17:07:05 +0000

Clipped from: www.hpcadvisorycouncil.com (share this clip)

One of the most exciting additions to ISC’12 this year is the Student Cluster Competition. The goal: derive the most possible application performance using less than 3000 watts.

The competition will feature small teams that compete to demonstrate the incredible capabilities of state-of- the-art high-performance cluster hardware and software. In a real-time challenge, teams of six undergraduate and/or high school students will build a small cluster of their own design on the ISC exhibit floor and race to demonstrate the greatest performance across a series of benchmarks and applications. The students will have a unique opportunity to learn, experience and demonstrate how high-performance computing influence our world and day-to-day learning. Held in collaboration of the HPC Advisory Council and ISC, the Student Cluster Competition is designed to introduce the next generation of students to the high performance computing world and community.

The Teams:

Karlsruhe Institute of Technology (Germany)

The University of Colorado (USA)

Stony Brook University (USA)

Tsinghua University (China)

NUDT (China)

Our intrepid reporter, Dan Olds will be there covering the play-by-play. Read the Full Story.

Webinar: NSF Big Data Solicitation May 21

Rich Brueckner — Sat, 19 May 2012 16:21:12 +0000

On May 21, The National Science Foundation and the National Institutes of Health will host a webinar on their joint Core Techniques and Technologies for Advancing Big Data Science & Engineering solicitation. This webinar is designed to describe the goals and focus of the BIGDATA solicitation, help investigators understand its scope, and answer any questions potential Principal Investigators may have.

The BIGDATA solicitation aims to advance the core scientific and technological means of managing, analyzing, visualizing, and extracting useful information from large, diverse, distributed and heterogeneous data sets so as to: accelerate the progress of scientific discovery and innovation; lead to new fields of inquiry that would not otherwise be possible; encourage the development of new data analytic tools and algorithms; facilitate scalable, accessible, and sustainable data infrastructure; increase understanding of human and social processes and interactions; and promote economic growth and improved health and quality of life.

Update: The webinar audio is now available for replay. Download the slides (PDF).

Interview: Author Rob Farber on the Secret Sauce for Programmers in the Kepler GPU

Rich Brueckner — Sat, 19 May 2012 15:51:06 +0000

www.youtube.com/watch?v=EoNnIVwW824

In this video, Rob Farber discusses new features in the Nvidia Kepler GPUs that make it easier for programmers to maximize application performance. Recorded at GTC 2012 in San Jose.

Farber’s book, CUDA Application Design and Development was the best-selling title at SC11 and at GTC 2012 this year. The book is designed to meet the needs of working software developers who need to understand GPU programming with CUDA and increase efficiency in their projects.

New Whitepaper: NVIDIA’s Next-Gen CUDA Compute Architecture – Kepler GK110

Rich Brueckner — Fri, 18 May 2012 17:12:35 +0000

If you still looking for more details on the new Kepler GPUs, Nvidia has stepped up with a new GK110 Architecture whitepaper for you.

Comprising 7.1 billion transistors, Kepler GK110 is not only the fastest, but also the most architecturally complex microprocessor ever built. Adding many new innovative features focused on compute performance, GK110 was designed to be a parallel processing powerhouse for Tesla and the HPC market. Kepler GK110 will provide over 1 TFlop of double precision throughput with greater than 80% DGEMM efficiency versus 60‐65% on the prior Fermi architecture. In addition to greatly improved performance, the Kepler architecture offers a huge leap forward in power efficiency, delivering up to 3x the performance per watt of Fermi.

Is the news all good? Blogger Paul Caheny writes that the K10 in particular continues a disturbing downward trend on memory capacity per FLOPs.

A couple of high level observations on how this fits into general HPC architecture trends. Firstly the ratio of memory capacity and memory bandwidth to compute is likely to continue to decrease, signifying the increasing necessity to make use of strong scaling in applications rather than the previously rich seam of weak scaling. K10 represents a more than 60% fall in Bytes/FLOPs (memory capacity per FLOPs) compared to M2090 and a reduction of 50% in Bytes/sec/FLOPs (memory bandwidth per FLOPs) compared to M2090 (both using SP FLOPs as per K10′s target market). It will be interesting to see what the corresponding numbers are for the upcoming K20.

Download the whitepaper (PDF).

IDC Breakfast Briefing at ISC’12 on June 18

Rich Brueckner — Fri, 18 May 2012 15:10:27 +0000

IDC will host its annual Analyst Briefing and Breakfast at ISC’12 on June 18 in Hamburg. You can join IDC’s Earl Joseph, Steve Conway, and Chirag Dekate as they present their expert insight and analysis on the evolving HPC market. This session will examine the drivers and inhibitors impacting the HPC Technical Server market and provide IDC’s latest forecasts.

The event starts at 8:00am in the CCH-Congress Center Hamburg (Hall B). Register now.

GPUs Power Penguin Computing, from HPC to Cloud and on to the Enterprise

Rich Brueckner — Thu, 17 May 2012 20:52:56 +0000

www.youtube.com/watch?v=SnkBg1KFce4

In this video, Tom Coull from Penguin Computing describes the company’s GPU-powered computing solutions for HPC. Penguin On Demand has offered GPUs in the Cloud for years, and the recent Kepler GPU announcement from Nvidia is figuring prominently in Penguin’s plans.

Coulll also describes Penguin Computing’s move to provide enterprise customers with the same powerful server and storage solutions that have powered its HPC customers.

End-users Need to Design Exascale Computers

Staff — Thu, 17 May 2012 19:46:02 +0000

It’s not size that counts but what you do with your supercomputer, delegates to the GPU Technology Conference in San Jose were told on 16 May.

End-user scientists and engineers need to get involved from the outset in the design of the next generation of machines – expected to be capable of delivering performance in the Exaflop range by the end of this decade – if they want the machines to produce useful scientific and engineering results.

Historically too much emphasis has been put on supercomputer hardware and not enough attention paid to the application software that would run on the machines to produce the results that scientists and engineers want. So during a session on ‘Exascaling your apps’, Steve Scott, the chief technology officer of Nvidia, which organised the conference, warned that if exascale machines were to have a broad impact: ‘We need a wake-up call.’ He did not think that system software would be an issue in the Exascale domain but rather: ‘I’m worried about application software.’

At present, no-one quite knows what the hardware will be for a successful Ex scale machine and this opens up an unprecedented opportunity for end users to get involved in ‘co-design’, Satoshi Matsuoka of the Tokyo Institute of Technology told the session. ‘Co-design will be the big key,’ he said. Because the architectures of the processors and the systems for Exascale computing are not yet fixed, he said, co-design is needed to reflect the needs of the end-user applications in the architectures themselves, right from the outset.

He pointed out that even at the Petaflop level, ‘It has been a challenge to run efficient applications. Scaling up has been a challenge because of the transition to many core and heterogeneous architectures.’ Steve Scott endorsed the point saying that although today’s applications will run on a future Exaflop machine: ‘Will they run well? No!’

The US Department of Energy has already set up three co-design initiatives, according to Jeff Vetter of Oak Ridge National Laboratory. They will be focusing on the areas of Combustion, Materials Science, and Nuclear Power. ‘In the past, the applications teams have been tossed new architectures and told to get on with it,’ he said. Now, in contrast, designers have to tell the users early on what the possibilities might be.

This story originally appeared on HPC Projects. It appears here as part of a cross-publishing agreement with Scientific Computing World.

GPUs Power Part-Time Scientists’ Plan for Lunar Rover Autonomy

Rich Brueckner — Thu, 17 May 2012 19:10:48 +0000

Today at the GTC 2012 conference, a team calling themselves the Part-Time Scientists presented plans for their GPU-powered lunar rover entry in the Google Lunar X Prize.

The autonomous navigation system of Asimov is a major technological leap. While the Russian Moon rovers Lunokhod 1 and 2 in the early 70s were fully controlled from Earth, today’s Mars rovers like NASA’s Mars Exploration Rover “Opportunity”, which has been tirelessly exploring the Red Planet since 2004, are autonomous. However, Opportunity requires nearly three minutes to process a pair of images – a delay that causes it to move at an average speed of just 1 cm/sec or less. New developments by the technology partnership between the DLR Institute of Robotics and Mechatronics (RMC) and the PTS have created, for the first time, an autonomous navigation system for a rover that has the capacity to process multiple images per second. The technology boosts a stereo camera that Asimov will use to calculate its own motion, generate a 2.5-dimensional environmental model, evaluate the site and determine a collision-free path – all in real time.

Read the Full Story.

GPU Proliferation in HPC Reflected in SC Conference Showfloor

Staff — Thu, 17 May 2012 14:54:15 +0000

Our GTC 2012 coverage continues with Dan Olds’s report on the rapid spread of Cuda and GPU computing. One measure is its increased presence the annual Supercomputing Conference series.

www.youtube.com/watch?v=eJu3l2mgOBs

This story is perhaps best told via pictures. In this first picture, we’re looking at the booth layout of the SC07 show floor in Reno. Like a typical SC show, there were a few hundred exhibitors ranging from hardware, software, and service vendors to academic institutions, research labs, and government research organizations. The sole presence of hybrid computing is the tiny green dot at the upper left of the schematic. It’s NVIDIA’s small booth – the lone beachhead for GPU-accelerated HPC. Fast-forward four years and… look at the progress. The SC11 show floor diagram is literally covered with green squares and rectangles.”

Read the Full Story.

Hybrid Computing’s Radical Growth

Staff — Wed, 16 May 2012 19:57:33 +0000

Our GTC 2012 coverage continues as Dan Olds examines the growth of the CUDA environment from 150,000 downloads in 2007 to 1.5 million today:

More importantly, there are 35 NVIDIA-fueled hybrid supercomputers on the Top500 list today. The NDUT Tianhe-1A system, with 14,300 CPUs and 7,100 NVIDIA GPUs, held down the top spot on the list in 2010. The upcoming Oak Ridge Titan system will sport more than 18,000 CPUs alongside 18,000 GPUs, and should become the fastest supercomputer in the world sometime this fall.”

Read the Full Story.

New Whitepaper: Dynamic Parallelism in CUDA

Rich Brueckner — Wed, 16 May 2012 19:48:19 +0000

The details on Dynamic Parallelism were hard to find after the new feature was introduced as part of the GTC 2012 keynote yesterday. Now Nvidia has followed up with a short whitepaper that describes how it works.

Dynamic Parallelism in CUDA is supported via an extension to the CUDA programming model that enables a CUDA kernel to create and synchronize new nested work. Basically, a child CUDA Kernel can be called from within a parent CUDA kernel and then optionally synchronize on the completion of that child CUDA Kernel. The parent CUDA kernel can consume the output produced from the child CUDA Kernel, all without CPU involvement.

Download the whitepaper (PDF).

Swimming in Sensors, Drowning in Data

Staff — Wed, 16 May 2012 16:42:10 +0000

Dan Olds from Gabriel Consulting Group shares his amazement from a GTC 2012 talk by MotionDSP.

Cleaning up and enhancing video is a tall order, compute-wise… But I just saw a demo of that in a GTC12 session run by MotionDSP. Their specialty is processing video streams from mobile platforms (think drones and airplanes) on the fly. We’re talking full motion, 30 frames per second video streams that are enhanced, cleaned up, and highly analyzable in real time. The amount of processing they’re doing is incredible. Lighting is enhanced, edges are enhanced, jitter is taken out, and the on-screen metadata (time, location, speed, etc.) is masked… The effect is profound. In the demo, what was once just a vague gray ship (which seemed to be vibrating like a can in a paint shaker) was clarified so that you could easily see what kind of ship it was and also see two suspicious figures milling around on deck. To me, it looked like there were enough pixels to enhance the video even further – to the point where we could identify the figures.”

Read the Full Story.