Today ISC 2016 announced the awards-winning research papers for the PRACE ISC Award and the Gauss Award.
“Today’s server systems provide many knobs which influence energy efficiency and performance. Some of these knobs control the behavior of the operating systems, whereas others control the behavior of the hardware itself. Choosing the optimal configuration of the knobs is critical for energy efficiency. In this talk recent research results will be presented, including examples of big data applications that consume less energy when dynamic tuning is employed.”
Mellanox announced today that it has joined the RISC-V foundation as a Founding Platinum Sponsor. The RISC-V foundation promotes the open RISC-V instruction set architecture and associated hardware and software ecosystem for a broad range of computing devices.
Today Bull Atos announced it has successfully installed the most powerful supercomputer in the Adriatic region. Named after the Croatia North Wind, the new Bura supercomputer at the University of Rijeka will be used in biotechnological and biomedical research and will be available to institutions and companies from abroad.
“EUROSERVER is an ambitious and holistic project aimed to arm Europe with leading technology for conquering the new markets of cloud computing. Data-centers form the central brains and store for the Information Society and are a key resource for innovation and leadership. The key challenge has recently moved from just delivering the required performance, to include consuming reduced energy and lowering cost of ownership. Together, these create an inflection point that provides a big opportunity for Europe, which holds a leading position in energy efficient computing and market prominent positions in embedded systems.”
In this video from the 2015 RubyConf event in Columbia, Ray Hightower presents: Parallella Supercomputing. “Parallella is a single-board supercomputer smaller than a deck of cards. While today’s fastest laptops contain four processor cores, Parallella has eighteen (2 ARM cores plus an Epiphany chip with 16 RISC cores). The maker of Parallella, Adapteva, is on a mission to democratize parallel computing. The company’s tag line is Supercomputing for Everyone.”
In this special guest feature, Robert Roe from Scientific Computing World reports that a new Exascale computing architecture using ARM processors is being developed by a European consortium of hardware and software providers, research centers, and industry partners. Funded by the European Union’s Horizon2020 research program, a full prototype of the new system is expected to be ready by 2018.
“It was indicated in my keynote this morning there are two really fundamental challenges we’re facing in the next two years in all sorts of computing – from supercomputers to cell phones. The first is that of energy efficiency. With the end of Dennard scaling, we’re no longer getting a big improvement in performance per watt from each technology generation. The performance improvement has dropped from a factor of 2.8 x back when we used to scale supply voltage with each new generation, now to about 1.3 x in the post-Dennard era. With this comes a real challenge for us to come up with architecture techniques and circuit techniques for better performance per watt.”
In this video from the 2015 Hot Chips Conference, Charles Zhang from Phytium presents: Mars – A 64-Core ARMv8 Processor. Formed in China in 2012, Phytium is a unique technology provider of HPC servers, focusing mainly on high performance general microprocessor, accelerator chip, reference board design and various servers design from blade, cluster, standard stack to HPC Server. “Optimized for HPC, the Mars chip features eight panels, each with eight “Xiaomi” cores. The panels share an L2 cache of 32 MB, two Directory Control Units and a routing cell for the internal mesh.”
Today the European Consortium announced a step towards Exascale computing with the ExaNeSt project. Funded by the Horizon 2020 initiative, ExaNeSt plans to build its first straw man prototype in 2016. The Consortium consists of twelve partners, each of which has expertise in a core technology needed for innovation to reach Exascale. ExaNeSt takes the sensible, integrated approach of co-designing the hardware and software, enabling the prototype to run real-life evaluations, facilitating its scalability and maturity into this decade and beyond.