Team applications are now being accepted for the SC17 Student Cluster Competition. “SC17 is excited to hold another nail-biting Student Cluster Competition, or SCC, now in its eleventh year, as an opportunity to showcase student expertise in a friendly yet spirited competition. Held as part of SC17’s Students@SC, the Student Cluster Competition is designed to introduce the next generation of students to the high-performance computing community.”
The European PRACE initiative has published a new Best Practice Guide for Intel Xeon Phi, Knights Landing Edition. “This best practice guide provides information about Intel’s MIC architecture and programming models for the Intel Xeon Phi co-processor in order to enable programmers to achieve good performance of their applications. The guide covers a wide range of topics from the description of the hardware of the Intel Xeon Phi co-processor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyze and improve the performance of applications.”
A technology-leading Fortune 100 company has deployed over 30,000 Supermicro MicroBlade servers, at its Silicon Valley data center facility with a Power Use Effectiveness (PUE) of 1.06, to support the company’s growing compute needs. Compared to a traditional data center running at 1.49 PUE, or more, the new datacenter achieves an 88percent improvement in overall energy efficiency. When the build out is complete at a 35 megawatt IT load power, the company is targeting $13.18M in savings per year in total energy costs across the entire datacenter.
In this video, researchers describe how the Tianhe-1 supercomputer supports scientific research. “Currently #43 on the TOP500, the 2.56 Petaflop Tianhe-1A carries out 1,400 computing tasks per day. It is mainly used to serve universities, research institutions, small and medium-sized enterprises, and provide scientific computing services.”
“A new data type called a “posit” is designed for direct drop-in replacement for IEEE Standard 754 floats. Unlike unum arithmetic, posits do not require interval-type mathematics or variable size operands, and they round if an answer is inexact, much the way floats do. However, they provide compelling advantages over floats, including simpler hardware implementation that scales from as few as two-bit operands to thousands of bits. For any bit width, they have a larger dynamic range, higher accuracy, better closure under arithmetic operations, and simpler exception-handling.”
Today the San Diego Supercomputer Center (SDSC) announced that the comet supercomputer has easily surpassed its target of serving at least 10,000 researchers across a diverse range of science disciplines, from astrophysics to redrawing the tree of life. “In fact, about 15,000 users have used Comet to run science gateways jobs alone since the system went into production less than two years ago.”
In this video from the IEEE Rebooting Computing Workshop, Dr. William Vanderlinde, Chief Scientist at Intelligence Advanced Research Projects Activity (IARPA), explains how we have already entered the era at the end of Moore’s law, including the end of Dennard Scaling. Dr. Vanderlinde also reviews the National Strategic Computing Initiative (NSCI) and IARPA’s focus in relation to the NSCI’s objectives.
In this video, Dr. Carl J. Williams, Deputy Director of the Physical Measurement Laboratory at the National Institute of Standards and Technology within the United States Department of Commerce, reviews the National Strategic Computing Initiative. Issued by Executive Order, the initiative aims to maximize benefits of high-performance computing research, development and deployment.
“The impending end of traditional MOSFET scaling has sparked research into preserving HPC performance improvements through alternative computational models. To better shape our strategy, we need to understand where each technology is headed and where it will be in a span of 20 years. This workshop brings together experts who develop or use promising technologies to present the state of their work, and spark a discussion on the promise and detriments of each approach.”
Applications that can take advantage of the new vectorization capabilities of the Intel Xeon Phi processor will show tremendous performance gains. “When considering vectorization, there are different tools that can assist the developer in determining where to look further. The first is to look at the optimization reports that are generated by the Intel compiler and then to also use the Vector Analyzer that can give specific advice on what to do to get more vectorization from the code.”