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Radio Free HPC Trip Reports from ASC16 & MSST

In this podcast, the Radio Free HPC team recaps the ASC16 Student Cluster Competition in China and the 2016 MSST Conference in Santa Clara. Dan spent a week in Wuxi interviewing ASC16 student teams, he came back impressed with the Linpack benchmark tricks from the team at Zhejiang University, who set a new student LINPACK record with 12.03 TFlop/s. Meanwhile, Rich was in Santa Clara for the MSST conference, where he captured two days of talks on Mass Storage Technologies.

Job of the Week: HPC Pre-Sales Engineer at SGI

SGI_logo_platinum_lgSGI is seeking an HPC Pre-Sales Engineer in our Job of the Week. “The HPC Pre-Sales Engineer role provides in depth technical and architectural expertise in Federal Sales opportunities in the DC area, primarily working with DOD and Civilian Agencies. As the primary technical interface with the customer, you must be able to recognize customer needs, interpret them and produce comprehensive solutions.”

Register for ISC 2016 by May 11 for Early Bird Discounts

There is still time to take advantage of Early Bird registration rates for ISC 2016. You can save over 45 percent off the on-site registration rates if you sign up by May 11. “ISC 2016 takes place June 19-23 in Frankfurt, Germany. With an expected attendance of 3,000 participants from around the world, ISC will also host 146 exhibitors from industry and academia.”

Video: Brendan Gregg Looks at Tools & Methodologies for Linux System Performance

In this video from the 2016 Percona Data Performance Conference, Brendan Gregg, Senior Performance Architect from Netflix presents: Linux Systems Performance. “Systems performance provides a different perspective for analysis and tuning, and can help you find performance wins for your databases, applications, and the kernel. However, most of us are not performance or kernel engineers, […]

Podcast: Supercomputing Gels with Stampede

In this TACC Podcast, Jorge Salazar looks at how researchers are using the Stampede supercomputer to shed light on the microscale world of colloidal gels — liquids dispersed in a solid medium as a gel. “Colloidal gels are actually soft solids, but we can manipulate their structure to produce ‘on-demand’ transitions from liquid-like to solid-like behavior that can be reversed many times,” Zia said. Zia is an Assistant Professor of Chemical and Biomolecular Engineering at Cornell University.

Submissions Open for Newly Merged TOP500 and Green500

Today the ISC Group announced that the Green500 will be integrated with the TOP500 project with a single submission process. “This merge is of great significance to the high performance computing community,” said Erich Strohmaier, co-founder of TOP500. “Both projects will now be maintained under a common set of rules for data submission, which will simplify the process for submitters and provide a consistent set of data for the historical record.”

Superfacility – How New Workflows in the DOE Office of Science are Changing Storage Requirements

Katie Antypas from NERSC presented this talk at the 2016 MSST conference. Katie is the Project Lead for the NERSC-8 system procurement, a project to deploy NERSC’s next generation supercomputer in mid-2016. The system, named Cori, (after Nobel Laureate Gerty Cori) will be a Cray XC system featuring 9300 Intel Knights Landing processors. The Knights Landing processors will have over 60 cores with 4 hardware threads each and a 512 bit vector unit width. It will be crucial that users can exploit both thread and SIMD vectorization to achieve high performance on Cori.”

Peta-Exa-Zetta: Robert Wisniewski and the Growth of Compute Power

While much noise is being made about the race to exascale, building productive supercomputers really comes down to people and ingenuity. In this special guest feature, Donna Loveland profiles supercomputer architect Robert Wisniewski from Intel. “In combining the threading and memory challenges, there’s an increased need for the hardware to perform synchronization operations, especially intranode ones, efficiently. With more threads utilizing less memory with wider parallelism, it becomes important that they synchronize among themselves efficiently and have access to efficient atomic memory operations. Applications also need to be vectorized to take advantage of the wider FPUs on the chip. While much of the vectorization can be done by compilers, application developers can follow design patterns that aid the compiler’s task.”

Basics For Coprocessors

“The Intel Xeon Phi coprocessor is an example of a many core system that can greatly increase the performance of an application when used correctly. Simply taking a serial application and expecting tremendous performance gains will not happen. Rewriting parts of the application will be necessary to take advantage of the architecture of the Intel Xeon Phi coprocessor.”

New Report Charts Future Directions for NSF Advanced Computing Infrastructure

A newly released report commissioned by the National Science Foundation (NSF) and conducted by National Academies of Sciences, Engineering, and Medicine examines priorities and associated trade-offs for advanced computing investments and strategy. “We are very pleased with the National Academy’s report and are enthusiastic about its helpful observations and recommendations,” said Irene Qualters, NSF Advanced Cyberinfrastructure Division Director. “The report has had a wide range of thoughtful community input and review from leaders in our field. Its timing and content give substance and urgency to NSF’s role and plans in the National Strategic Computing Initiative.”