Today Cray introduced new performance breakthroughs that will provide customers with the fastest Cray XC supercomputers and Cray Sonexion storage systems to date. “Our customers are taking on increasingly complex computational problems that are expanding the boundaries of supercomputing and storage performance capabilities,” said Ryan Waite, Cray’s senior vice president of products. “We partner closely with our customers to understand their unique requirements and deliver new systems that deliver peak performance. For many of our customers, Intel Xeon Phi processors and Lustre parallel file systems are critical components of their supercomputing infrastructure. Our close collaboration with Intel helps to ensure our Intel Xeon Phi processor-based solutions scale to the most demanding performance requirements and our close partnership with Seagate helps scale Lustre to new levels of performance and stability.”
SuperMicro is showcasing its High Performance Computing solutions at ISC 2016 this week in Frankfurt, Germany. “With Supermicro HPC solutions deep learning, engineering, and scientific fields can scale out compute clusters to accelerate their most demanding workloads and achieve fastest time-to-results with maximum performance per watt, per square foot, and per dollar,” said Charles Liang, President and CEO of Supermicro. “With our latest innovations incorporating Intel Xeon Phi processors in a performance and density optimized Twin architecture, 8-socket scalable servers, 100Gbps OPA switch for high bandwidth connectivity, and high-performance NVMe for Lustre based storage, our customers can accelerate their applications and innovations to address the most complex real world problems.”
Today Cray announced that the company has been awarded new contracts for its Cray XC40 supercomputer, two Cray CS400 cluster supercomputers, a Cray Urika-GX agile analytics platform, and its DataWarp applications I/O accelerator to customers in Japan, the United Kingdom, and the United States.
Today Univa announced the release of Univa Grid Engine Version 8.4.0 with preview support for the Intel Xeon Phi processor (formerly code-named “Knights Landing”), enabling enterprises to launch and control jobs on Intel Xeon Phi processor-based systems. The update simplifies running and managing applications on Intel Xeon Phi processor-based clusters.
Today EXTOLL in Germany released its new TOURMALET high-performance network chip for HPC. “The key demands of HPC are high bandwidth, low latency, and high message rates. The TOURMALET PCI-Express gen3 x16 board shows an MPI latency of 850ns and a message rate of 75M messages per second. The message rate value is CPU-limited, while TOURMALET is designed for well above 100M msg/s.”
Today ASRock Rack announced plans to showcase its 2U and 3U systems for the HPC market at ISC 2016. “First of all, ASRock Rack is showing its new product 3U16N, which is by far the highest-density among all the microservers features with Intel Xeon D processors. With multiple computing nodes, this microserver can easily handle intensive critical tasks under low power consumption.”
The vector parallel capabilities of the Intel Xeon Phi coprocessor are similar in many ways with vectorizing code for the main CPU. The performance improvement when coding smartly and using the tools available can be tremendous. Since the Intel Xeon Phi coprocessor can show very large gains in performance due to its extra wide processing units. “Although it is time consuming to look at each and every loop in a large application, by doing so, and both telling the compiler what to do, and letting the compiler do its work, performance increases can be quite large, leading to shorter run times and/or more complete results.”
With the release of a Developer Access Program for the Intel Xeon Phi Processor codenamed Knights Landing, Intel and its partner Colfax are widening early levels of access, support and training for the widely anticipated next-generation Intel Xeon Phi processor release. The Developer Access Program gives developers the opportunity to begin leveraging key new capabilities in the processor before they are generally available. That means developers will have time to work to parallelize and vectorize their code and look for opportunities to exploit the massive performance capabilities that KNL offers so workloads are ready for prime time when customers deploy their next-generation systems.
Today the Numerical Algorithms Group (NAG) has announced the NAG Software Modernization Service. The new service solves the porting and performance challenges faced by customers wishing to use the capabilities of modern computing systems, such as multi-core CPUs, GPUs and Xeon Phi. NAG HPC software engineering experts modernize the code to enable portability to appropriate architectures, optimize for performance and assure robustness.
Intel is offering a 4-part summer series of developer training workshops at Stanford University to introduce high performance computing tools.