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Video: Panel Discussion on Exascale Computing

In this video from the 2016 Stanford HPC Conference, Gilad Shainer from the HPC Advisory Council moderates a panel discussion on Exascale Computing. “Exascale computing will uniquely provide knowledge leading to transformative advances for our economy, security and society in general. A failure to proceed with appropriate speed risks losing competitiveness in information technology, in our industrial base writ large, and in leading-edge science.”

EXTOLL Deploys Immersion Cooled Compute Booster at Jülich

Today Extoll, the German HPC innovation company, announced that is has it has successfully implemented its new GreenICE immersion cooling system at the Jülich Supercomputing Centre. As part of the DEEP Dynamical Exascale Entry Platform project, GreenICE was developed to meet the need for increased compute power, density, and energy efficiency.

UCX: An Open Source Framework for HPC Network APIs and Beyond

“Unified Communication X (UCX) is a set of network APIs and their implementations for high performance computing. UCX comes from the combined efforts of national laboratories, industry, and academia to co-design and implement a high-performing and highly scalable communication APIs for next generation applications and systems. UCX solves the problem of moving data memory location “A” to memory location “B” considering across multiple type of memories (DRAM, accelerator memories, etc.) and multiple transports (e.g. InfiniBand, uGNI, Shared Memory, CUDA, etc. ), while minimizing latency, and maximizing bandwidth and message rate.”

Video: Programming Models for Exascale Systems

“This talk will focus on programming models and their designs for upcoming exascale systems with millions of processors and accelerators. Current status and future trends of MPI and PGAS (UPC and OpenSHMEM) programming models will be presented. We will discuss challenges in designing runtime environments for these programming models by taking into account support for multi-core, high-performance networks, GPGPUs, Intel MIC, scalable collectives (multi-core-aware, topology-aware, and power-aware), non-blocking collectives using Offload framework, one-sided RMA operations, schemes and architectures for fault-tolerance/fault-resilience.”

Exascale Architectures: Evolution or Revolution?

In this special guest feature, Earl Joseph from IDC describes his SC15 panel where four HPC luminaries discussed, disputed, and divined the path to exascale computing. “As the panel wound to a close, participants agreed on one thing: the path to exascale contains significant obstacles, but they’re not insurmountable. Tremendous progress is being made in preparing codes for the next generations of systems, and sheer determination and innovation is running at an all-time high.”

ISC 2016 Keynote to Showcase Women’s Excellence in Computational Science

Today the ISC 2016 conference announced that their Tuesday keynote session will highlight contributions from female researchers and scientists in advancing the field of computational science. “This year, Dr. Jacqueline H. Chen, a distinguished member of technical staff at Sandia National Laboratories, has been invited to keynote on Tuesday, June 21, on the topic of advancing the science of turbulent combustion using petascale and exascale simulations.”

Agenda Posted: HPCAC Swiss Conference in Lugano, March 21-23

The HPC Advisory Council has posted the speaker agenda for the HPCAC Swiss Conference. The event takes place March 21-23 in Lugano, Switzerland. The conference will focus on High-Performance Computing essentials, new developments and emerging technologies, best practices and hands-on training.

Creating an Exascale Ecosystem Under the NSCI Banner

“We expect NCSI to run for the next two decades. It’s a bit audacious to start a 20 year project in the last 18 months of an administration, but one of the things that gives us momentum is that we are not starting from a clean sheet of paper. There are many government agencies already involved and what we’re really doing is increasing their coordination and collaboration. Also we will be working very hard over the next 18 months to build momentum and establish new working relationships with academia and industry.”

ExaNeSt European Consortium to Develop Exascale Architecture

In this special guest feature, Robert Roe from Scientific Computing World reports that a new Exascale computing architecture using ARM processors is being developed by a European consortium of hardware and software providers, research centers, and industry partners. Funded by the European Union’s Horizon2020 research program, a full prototype of the new system is expected to be ready by 2018.

European ExaNeSt Project to Pave the Way to Exascale

Today the European Consortium announced a step towards Exascale computing with the ExaNeSt project. Funded by the Horizon 2020 initiative, ExaNeSt plans to build its first straw man prototype in 2016. The Consortium consists of twelve partners, each of which has expertise in a core technology needed for innovation to reach Exascale. ExaNeSt takes the sensible, integrated approach of co-designing the hardware and software, enabling the prototype to run real-life evaluations, facilitating its scalability and maturity into this decade and beyond.