As El Reg anticipated earlier this week, the new upper management at AMD has come to its senses and figured out that moving to a new core and two new sockets for its Opteron line in 2012 was not a particularly good idea for its own finances, or those of the server makers who it wants to peddle Opteron-based iron. And so, that plan has been scrapped.

Instead, AMD is going to field new 32 nanometer processors based on the forthcoming “Piledriver” core design and jam them into the same G34 and C32 sockets, meaning that HP, Dell, Super Micro, IBM, Acer, and a handful of other box makers will not have to engineer new motherboards and systems.

AMD CEO Rory Read, formerly of IBM and Lenovo, spoke at the company’s analyst day in Silicon Gulch on Thursday and said that the company sees that “proprietary control points” were breaking down and that AMD was chasing “inflection points” in the PC, tablet, and server spaces. He explained AMD would bring its expertise in CPU and GPU design together to crafty system-on-chip (SoC) products that will, presumably, also integrate network and other types of I/O directly on the chip.

“Shift happens, shift is good,” Read stated emphatically, and with a straight face, adding that AMD was being tweaked to become a “market driven company” and not second fiddle in an “unhealthy duopoly.” The task Read sees ahead for AMD is “about stepping out of the shadows and leading.”

But, according to Read and Lisa Su (a semiconductor researcher at IBM and former CTO at Freescale Semiconductor who was hired back in December to be senior vice president and general manager of the new Global Business Units,) what AMD needs to do right now in servers is to step back, ramp up production of Opteron 4200 and 6200 processors and rebuild and extend relationships with server makers as it plots out its future Opteron chips.

Sticking with the existing C32 sockets for the Opteron 4200 sockets and the G34 sockets for the Opteron 6200s is just part of listening to the customer. It also gives AMD some engineering breathing time to come up with interesting, low-power Opteron platforms that are tailored specifically for hyperscale Web, big data, server virtualization, database, and similar workloads where AMD’s Opterons do well.

“Server is a great opportunity for us, and it is clear that our market share is not very high today,” conceded Su. But she also said that the “Bulldozer” core and its different architecture takes time to get its footing. Considering this, introducing new sockets right now was a bad idea technically and economically for both AMD and server makers. “At the end of the day, that wasn’t the right answer for our customers,” Su said.

Back in November 2010, two months before CEO Dirk Meyer was ousted, the plan was to crank up the Opteron 6200s to 20 cores using the new Piledriver core, an improved version of the current “Bulldozer” core used in the Opteron 4200 and 6200 server processors as well as a number of desktop chips.

The plan called for the “Sepang” processor to have up to ten Piledriver cores and plug into the C32 sockets, which are used to make servers with one or two sockets across a single memory space. The “Terramar” Opteron chip was the kicker to the current Opteron 6200 and would put two of these Sepang chips in a single package and scale it up to 20 cores per socket. Both of these chips were implemented in the 32 nanometer silicon-on-insulator (SOI) processes from fab partner GlobalFoundries.

A year later, with microservers taking off (at least in terms of marketing hype), AMDannounced that it would chase microserver builders with a new single-socket Opteron 3000 chip, code-named “Zurich,” that plugged into the AM3+ socket. The Zurich chip is a variant of the Opteron 4200 with four or eight cores activated, one HyperTransport link, and – most importantly – availability in less expensive motherboards.

The Zurich chip, presumably to be called the Opteron 3200, was expected sometime in the first half of 2012 when AMD was talking about it last fall, but it is now going to be launched in the first quarter, as you can see in the roadmap below:

For larger Opteron systems, AMD is taking a conservative approach. Rather than adding two more cores to the basic Opteron processor unit, the new “Seoul” processor keeps the core count at six or eight as the new Piledriver core is brought in. The DDR3 main memory stays the same – two channels per socket – as with the current Opteron 4200s, and the chips will not include any additional on-chip I/O, such as the PCI-Express 3.0 links that Intel is putting on its forthcoming “Sandy Bridge” family of Xeon E5 processors for machines with one, two, or four sockets.

The high-end “Abu Dhabi” Opterons will have 4, 8, 12, and 16 Piledriver cores, the same core count as the Opteron 6200s that started shipping last summer, and will sport the same four channels of DDR3 memory per socket.

You’ll notice that AMD is not talking about how many HyperTransport links will be on these future Piledriver-based Opterons or what speed they will run at, so it makes perfect sense to conjecture that they will run at a faster rate – 8GT/sec sounds reasonable to match the expected 25 per cent increase in raw performance that AMD was promising for Piledriver cores in desktop processors.

AMD is also expecting to put out a kicker for the Opteron 3200, dubbed “Delhi” and offering four or eight Piledriver cores.

All of the new Opterons will be etched in GlobalFoundries’ 32 nanometer processes, just like the current ones are. On the desktop processor roadmaps that Su went over, the chips for 2012 and those for 2013 were clearly marked. Not so on the server chip roadmaps, but we placed a call to AMD and were told by a spokesman that all of the chips above will be coming out this year. The Abu Dhabi and Seoul Opterons are due towards the end of the year.

The big change, according to new AMD CTO Mark Papermaster, formerly of IBM, Apple, and Cisco Systems, was that AMD was shifting from a design philosophy that focused in the performance of processor cores, adopted the bleeding edge tech from GlobalFoundries or Taiwan Semiconductor Manufacturing Corp to try to compensate for the process lag AMD (and everyone else) has with Intel.

This lead to execution problems, and more importantly, Papermaster said that the company’s current managers do not believe that the process technology node trumps integration of functions on an SoC and the “experience” that the user has using a device based on AMD silicon.

Su didn’t give out a lot of details on the future Piledriver cores, except to say that it would be able to do more instructions per cycle and would have higher clock frequencies. Many had expected for Bulldozer to do better on the clock speed front.

Looking out further into the future, AMD is cooking up a third generation modular core called “Steamroller,” which would have a greater level of parallelism. This could mean a lot of different things, such as adding more threads or cores to the chip or adding more instruction units per core module. Su did not say, and it is likely that AMD is itself not quite sure what it means. And further out beyond that, AMD will crank out more performance in some unspecified way with a modular core design called “Excavator.”

It will be interesting to see what AMD integrates onto its server chips and how fast it can do it. In the meantime, Intel is going to make plenty of hay in the supercomputing market where there are workloads with heavy I/O demands because it can support PCI-Express 3.0 peripherals with the future Xeon E5 processors. It remains to be seen how much of an advantage this will be across the server market at large. ®

Analysis If you want to get into the server processor racket, here’s some advice: Don’t bring a knife to a gun fight. And when you whip out your guns, you better have a piece stashed in each of your boots, maybe another high-caliber rifle on your back, and a few knives while you are at it for price-cutting when the bullets run out.

With Intel getting ready to launch its “Sandy Bridge” Xeon E5 processors in March and revving up its 22 nanometer processes to eventually field “Ivy bridge” kickers, Advanced Micro Devices is going to have to engineer some pretty impressive new Opteron server chips. It’ll have to cook up those chips pretty sharpish, in conjunction with its wafer-baking partners, if it hopes to gain ground in the ongoing x86 server chip war – much less hold the hard-fought ground it has attained in high performance computing and server virtualization.

Back in the early 2000s, Intel was trying to protect its high-end 64-bit Itanium server business and push its Xeon processors down into the 32-bit volume server space, and AMD brilliantly shot the gap between the Xeon and Itanium to create the 64-bit Opterons, eventually pushing its server market share as high as 25 per cent.

But it has been a long time since x86 server chip juggernaut Intel was hammered – SledgeHammered, to be specific – by longtime rival AMD with its 64-bit, low-power, multicore Opteron processors. Intel shifted to the Core microarchitecture, added 64-bit memory addressing and processing, and a slew of key features such as the QuickPath Interconnect to its Xeon processors and hit back hard against the Opteron upstart. The “Nehalem” Xeon architecture announced in 2009 had everything that Opterons had, and when the Great Recession hit just in the wake of yet another Opteron delay, server makers put most of their effort into build Xeon war machines, not Opteron battlewagons, and AMD has been losing ground ever since.

Because server chip profits help pay the bills at Intel, AMD, IBM, Oracle, and Fujitsu, the loss of market share by AMD is one of the key reasons why CEO Dirk Meyer resigned in January 2011. In hindsight, we can also see that Meyer and the bulk of the management team that handles chip development and manufacturing have been replaced since new CEO Rory Read came aboard last July. AMD has a new CTO – Mark Papermaster, formerly of IBM, Apple, and Cisco Systems – and has replaced its former marketing, products, and operations bosses, and has tapped ex-Intel engineer Rajan Naik as senior vice president and chief strategy officer.

So, AMD is no doubt drawing up new war plans for the x86 server battlefield, but the company has not said much to date about its plans. Perhaps it will enlighten us during its Analyst Day this week. But we can conjecture about what AMD might do by looking at what Intel is about to do in the x86 racket.

A Sandy Bridge not too far

While Intel never publicly promised that the “Sandy Bridge-EP” Xeon E5 processors would launch last fall for shipments in the fourth quarter, the circumstantial evidence – and comments from motherboard and server makers like Super Micro – indicate that this was indeed the plan. But with AMD having its own issues shipping its “Interlagos” Opteron 6200 processors for two-socket and four-socket servers and its “Valencia” Opteron 4200s for single-socket and dual-socket machines, Intel did not have to rush to market. (The speculation is that a SAS controller bug similar to the one in the C200 chipset that delayed the launch of “Sandy Bridge-DT” E3 processors and various PC chips of similar design has been found in the “Patsburg” C600 chipset for the Xeon E5s. Intel has not confirmed this.) Frankly, with Intel turning in the best fourth quarter and fiscal year in its history, in terms of profits and revenues, as 2011 came to a close, despite a PC slowdown and whatever issues stalled the Xeon E5s, it is hard to argue that Intel made the wrong call.

Chip happens

Intel is just starting to talk to press and analysts under embargo this week about the forthcoming Xeon E5s, and it is no coincidence that it is doing so just ahead of AMD’s Analyst Day. (El Reg is reporting this to you from coach on a Delta flight to Portland, Oregon, ahead of a briefing by Intel from its Beaverton chip and server development labs.)

As El Reg exclusively disclosed last May, the plan with the Xeon E5s is to take what would have normally been a chip for general-purpose two-socket workhorses and bifurcate the line into multiple processor and chipset variants to address very precise market segments. This is, of course, what AMD did two years when it created two different two-socket server families: the Opteron 4100s – which could also scale down to single socket machines aimed at small, power-sensitive workloads – and the Opteron 6100s, which could scale up to four processor sockets.

Anything AMD can do, Intel can do. (The market decides if Intel can do it better, or at least well enough to allow IT managers to fall back on the “nobody ever got fired for buying Intel” insurance policy.)

Intel is actually cutting its server market into eight pieces with the Xeon E5 launch. That’s Itanium 9300s and Xeon 7500s and E7s at the high-end (and eventually the “Sandy Bridge-EX” E8s). That’s two segments of the market that share chipsets and memory cards, but that have different motherboards and sockets. At least until Intel finally delivers, as it is rumored to be in the works, the long-promised common Xeon-Itanium socket. That could happen with the E8s, but it is far more likely to happen with the “Ivy Bridge-EX” Xeon E9s years hence. At the low-end, there’s the single-socket Xeon E3 and Atom processors, depending on how wimpy or brawny your workload is. That’s four addressable server segments in total.

The Xeon E5s will also span four different server types and will cover the middle and overlap with the high and low ends. The Xeon E5-2600, as the first of the “Romley” server platforms are expected to be called, will use the “EP” variant of the Xeon E5 chip that plugs into the new “Socket R” CPU socket. This socket is not compatible with the current Xeon 5500 and 5600 processors, but has all sorts of goodies, including two QPI links between the processors, support for unregistered, registered, and load-reduced (LR) DDR3 main memory, and integrated PCI-Express 3.0 controllers on the processor. This is the chip that Intel has presumably been shipping under NDA to selected supercomputer and hyperscale data center customers since last fall. This chip is clearly aimed at two-socket Opteron 6200 machines.

For two-socket machines that don’t need all of these capabilities, Intel is expected to roll out its “Sandy Bridge-EN” chips, rumored to be called the Xeon E5-2400s. These chips will plug into the new “Socket B2″ socket and will sport only one QPI link between processors as well as fewer memory channels, fewer DIMMs per core, and fewer PCI-Express 3.0 slots. This chip is fired directly at two-socket Opteron 4200 iron.

If the rumors are right, then Intel will also ship a variant of the Sandy Bridge-EP chip that will be able to span four processor sockets in a single system image. This chip is expected to be called the Xeon E5-4600 and is obviously targeting the four-socket Opteron 6200.

And finally, Intel will field a Xeon E5-1600 chip, aimed at single-socket servers and workstations and based on the Sandy Bridge-EN chip that will zero in on single-socket Opteron 4200 servers and whatever plans AMD has to revive its single-socket server biz with the Opteron 3000 series, which it said it was working on back in November. The first Opteron 3000 chip, code-named “Zurich” and presumably to be named the Opteron 3200 to be consistent with the 2012 series of Opteron processors, is basically a cut-down Opteron 4200 with six or eight cores that will plug into an AM3+ socket instead of a C32 socket.

In any event, Intel appears to be looking to chase the microserver segment with the Xeon E5-1600 as AMD is looking to pursue with the Opteron 4200 and 3200 chips. The word on the street is that the Xeon E5-1600 will plug into the Socket R socket, but it would make more sense for it to use the lower-cost Socket B2 socket.

Should all of this come to pass in 2012, it is safe to say that Intel has a weapon to match everything that AMD can throw at it – and then some. AMD only has one flavor of four socket machine, and Intel has three if you count Itanium. AMD has only two kinds of single-socket boxes it can bring into the field, Intel has three if you count Atom. AMD has two two-socket boxes, but Intel has four if you count Itanium.

It’s Hammer time, again

It must have been such fun to run AMD when Intel’s server and PC chips were misaligned with the market needs. It must be daunting to come into work every day at AMD and see the lead in process technology, cash, clout, and chip and market coverage that Intel currently has not just over AMD, but over anyone who is making processors for anything larger than a smartphone or tablet.

AMD has also been winning the core count skirmish against Intel and positioning its two-core “Bulldozer” module used in the Opteron 4200s and 6200s as two strong physical threads against Intel’s weaker HyperThreaded cores. However, with a shared scheduler, on workloads that make heavy use of 256-bit floating point instructions, half of the 16 cores in an Opteron 6200 will often sit idle and the net effect is that the performance should be about the same as the forthcoming Xeon E5 with eight cores running 256-bit floating point. AMD has two stronger cores, but only if you want to do 128-bit math or integer work.

So what is AMD to do?

Go back to the drawing board and exploit whatever weaknesses it can find in Intel’s armor, just as always. Or, start a fight on a new battlefield where Intel is not going to be so strong.

Back in November 2010, two months before the management shakeup at AMD, the company said that its plan for this year was to bring out replacements for the C32 socket used for Opteron 4100 and 4200 processors and the G34 socket used with Opteron 6100 and 6200 processors.

The plan calls for the high-end Opterons, code-named “Terramar” and presumably called the Opteron 6300, to have 20 Bulldozer cores based on a next-generation core, code-named “Piledriver”. The low-end will get the “Sepang” Opteron 4300, a ten-core chip that is essentially what gets double-stuffed into a socket to make the Terramar chip package. Rumor has it that AMD will boost memory capacity with these forthcoming Opterons as well as support PCI-Express 3.0 peripherals. The Terrarmar and Sepang chips will be etched in the 32 nanometer processes used by GlobalFoundries, AMD’s spun out former chip manufacturing operations.

Presumably there is a process shrink to 28 nanometers to boost clock speed and therefore single-threaded application performance of these Opteron 4300 and 6300 chips in the works, but AMD has not said yet and will no doubt lay out its plans at Analyst Day this week.

As was the case during the Great Recession, now would be a particularly bad time for AMD to force a socket transition onto its smaller band of server customers, and the new management at AMD must be looking pretty hard at that roadmap, wondering if they can change as little as possible now to buy time to do a lot more radical engineering for the future.

If I were running AMD, I would be looking very hard at that “Bobcat” core that is the alternative to Intel’s Atom and start thinking about servers, and also go back and look at the“Trinity” low-power Fusion chip, which is based on the Bulldozer cores.

When AMD was kicking Intel in the chips in the mid-2000s, Chipzilla relatively quickly (okay, it took years) shifted over to the Core laptop chip architecture for its PCs and servers and not only saved its chip business, but blunted the AMD attack. Intel has copied most of the ideas that made the Opteron better or different and is now using its wafer-baking process technology and its ability to set market prices to force AMD to compete mostly on lower price for roughly equivalent performance and features.

This is not an enviable position to be in for AMD, obviously. But there’s always the ARM option, and AMD could do something radical like buy Applied Micro or Calxeda and turn the x86 chip war into a two-front war for Intel to have to fight. ®

This article originally appeared in The Register. It appears here in its entirety as part of a cross-publishing agreement.

Intel has made no secret that it wants to bolster its Data Center and Connected Systems business by getting network equipment providers to use Xeon processors inside of their networking gear – that Intel division posted $10.1bn in revenues in 2011, and the company wants to break $20bn in the next five years.

Last July, Intel paid an undisclosed amount to get its hands on Fulcrum Microsystems, a maker of the FocalPoint family of ASICs for Ethernet switches and routers that run at 10GbE and 40GbE speeds. Fulcrum’s most famous customer was Arista Networks, the low-latency networking switch-maker founded by Sun Microsystems cofounder Andy Bechtolsheim. Intel never said what it paid for Fulcrum, but the company had raised $102m in venture capital since it was founded, and the price was very likely a multiple of that figure.

Despite the improvements in 10GbE and 40GbE switch chips over the past several years, InfiniBand still has important niches where even lower latency and still higher bandwidth are crucial – the supercomputing racket, for instance, or in database clustering. Just ask Oracle, which uses InfiniBand silicon from Mellanox Technologies in its Exadata database clusters and Exalogic web application server clusters, and which took a 10.2 per cent stake in the chip and switch-maker back in October 2010.

At the time, Mellanox assured Wall Street that Oracle had no intention of taking over the chipmaker, but with QLogic’s upstart InfiniBand biz snapped up by Intel, some systems or networking companies might now be tempted to take a run at Mellanox. But if Oracle or IBM or Cisco Systems are tempted to eat Mellanox, all that will do is eventually drive everyone into the loving arms of Intel, with its own Ethernet or InfiniBand ASICs. So, in a funny way, Intel is probably praying that someone does eat Mellanox.

And the funniest thing of all would be if AMD actually woke up and smelled the systems biz, and did it. By doing so, AMD would have the SwitchX two-timing Ethernet and InfiniBand ASICs and the ConnectX-3 switch-hitting server adapters, and could start integrating these deeper into its chipsets and eventually onto its chips.

Intel and InfiniBand go way back

InfiniBand has its roots in the Next Generation I/O project supported by Intel, Sun Microsystems, and Microsoft, along with the Future I/O alternative supported by IBM, Compaq, and HP. These specs were merged back in 1999, with Intel and IBM largely steering the process.

The idea was to provide a single switched fabric that would link computers and storage to each other from the desktop to the data center, and be an alternative to Ethernet networks for server-to-server and PC-to-server links, and to PCI-Express and Fibre Channel for linking peripherals.

Academically, InfiniBand was probably the right answer for a unified switch fabric – but markets don’t study in schools, they live on the mean streets and give and take hard knocks. And thus, InfiniBand has been relegated to a niche and, more importantly, the key technologies that made InfiniBand better, stronger, and faster than Ethernet have been borged onto Ethernet, closing the gap.

For now, Intel is saying that its acquisition of the InfiniBand chip, adapter, and switch business from QLogic is all about HPC, but it may be looking further down the road, when PCI-Express runs out of gas.

“At the International Supercomputing Conference 2011, Intel unveiled a bold vision to redefine HPC performance and break the exascale barrier by 2018,” said Kirk Skaugen, the outgoing general manager of Intel’s Data Center and Connected System Group, said in a statement. “The technology and expertise from QLogic provide important assets to provide the scalable system fabric needed to execute on this vision. Adding QLogic’s InfiniBand product line to our networking portfolio will bring increased options and exceptional value to our datacenter customers.”

Last week, Skaugen – who has been pushing Intel’s expansion into switching and storage chippery for the past several years – was tapped to run Chipzilla’s PC Client Group. Diane Bryant, who has worked for Skaugen in the past and who was most recently Intel’s CIO, has replaced Skaugen and will be driving Intel’s server, storage, and networking strategies.

By selling its InfiniBand biz to Intel, QLogic will be able to double down on its Fibre Channel and Ethernet switches and adapters. QLogic has had some success with its InfiniBand gear, landing the 2,000-node “Sierra” cluster with Dell at Lawrence Livermore National Labs and also being the switch supplier for the 20,000-node procurement awarded to Appro International last June by the US Department of Energy’s Tri-Labs: Lawrence Livermore, Los Alamos, and Sandia National Laboratories.

“The sale of these InfiniBand assets will benefit our shareholders by enabling us to provide better focus and greater investment in growth opportunities for the data center with our converged networking, enterprise Ethernet, and storage area networking products,” said QLogic’s president and CEO, Simon Biddiscombe, in his statement. “After the sale, our cash position will be further strengthened and we expect the impact on earnings per share to be neutral. In addition, the sale of these assets to a leading technology innovator and recognized HPC leader will provide a greater investment stream in high performance fabrics for InfiniBand partners and customers.”

Speaking to El Reg two weeks ago apropos of nothing about the InfiniBand racket, QLogic’s head of global alliances and solutions marketing for HPC Joe Yaworksi said that the reason why QLogic was winning more InfiniBand deals is that its TruScale chips offer better performance running at Quad Data Rate (QDR) 40Gb/sec speeds than do Mellanox’ SwitchX products running at Fourteen Data Rate (FDR) 56Gb/sec speeds.

The big reason for this, said Yaworksi, was that QLogic bought compiler-maker PathScale in early 2006, and it has a networking stack that was designed to handle millions of messages per second. (PathScale was sold to SciCortex in 2007, and when it went bust, Cray picked up the PathScale pieces in 2009 and an open source PathScale has emerged from the ashes with a license from Cray.) The combination of the TruScale InfiniBand ASICs and PathScale messaging stack and compilers is what gave QLogic the idea it could take on Mellanox and win.

Yaworksi told El Reg that QLogic was “taking a hard look at whether or not we will ship FDR InfiniBand,” although with Intel picking up the company, there will be more funds to do whatever might seem appropriate. The company was thinking that in the second half of 2013 or the first half of 2014 it might jump straight to Eight Data Rate (EDR) speeds, which runs the InfiniBand lanes at 25Gb/sec.

That would be a long time to wait between products and to live on QDR, and a gap that Intel is probably not likely to tolerate. But it all depends on what Intel’s plans are, and the company isn’t saying anything right now. If QLogic weren’t a public company, both would have probably said less.

Intel expects the QLogic InfiniBand deal to close by the end of March, and added that a “significant number” of the employees associated with the business were expected to accept job offers from Chipzilla. ®

This article originally appeared in The Register. It appears here in its entirety as part of a cross-publishing agreement.