“The next flagship supercomputer in Japan, replacement of K supercomputer, is being designed toward general operation in 2020. Compute nodes, based on a manycore architecture, connected by a 6-D mesh/torus network is considered. A three level hierarchical storage system is taken into account. A heterogeneous operating system, Linux and a light-weight kernel, is designed to build suitable environments for applications. It can not be possible without codesign of applications that the system software is designed to make maximum utilization of compute and storage resources. “
“As a research area, quantum computing is highly competitive, but if you want to buy a quantum computer then D-Wave Systems, founded in 1999, is the only game in town. Quantum computing is as promising as it is unproven. Quantum computing goes beyond Moore’s law since every quantum bit (qubit) doubles the computational power, similar to the famous wheat and chessboard problem. So the payoff is huge, even though it is expensive, unproven, and difficult to program.”
In this special guest feature, John Kirkley writes that Argonne is already building code for their future Theta and Aurora supercomputers based on Intel Knights Landing. “One of the ALCF’s primary tasks is to help prepare key applications for two advanced supercomputers. One is the 8.5-petaflops Theta system based on the upcoming Intel® Xeon Phi™ processor, code-named Knights Landing (KNL) and due for deployment this year. The other is a larger 180-petaflops Aurora supercomputer scheduled for 2018 using Intel Xeon Phi processors, code-named Knights Hill. A key goal is to solidify libraries and other essential elements, such as compilers and debuggers that support the systems’ current and future production applications.”
Registration opened today for the ISC 2016 conference, which takes place June 19-23 in Frankfurt. This year, the ISC 2016 conference program features an increased focus on Cloud, Machine Learning, and Robotics. In fact, insideHPC has learned that bulk of topics normally covered at the annual ISC Cloud conference have been absorbed into the ISC High Performance industry track. To learn more, we caught up with Wolfgang Gentzsch, a member of the ISC Steering Committee who has chaired the ISC Cloud event since its beginnings.
Scientists have developed a process to deposit nano-lasers directly onto silicon chips, paving the way for fast and efficient data processing using silicon photonics. Physicists at the Technical University of Munich (TUM) have developed a nano-laser one thousand times thinner than a human hair. This process deposits the nano-wire lasers directly onto the chip, making it possible to produce high-performance, cost-effective photonic components.
The US Department of Commerce has released details of the President’s budget request for the National Institute of Standards and Technology (NIST) in 2017 – proposing to increase spending on HPC and future computing technologies by more than 50 per cent. The total discretionary request for NIST is $1 billion, a $50.5 million increase in the enacted amount from 2016. The funding supports NIST’s research in areas such as computing, advanced communications and manufacturing.
In this special guest feature from Scientific Computing World, Andrew Jones from NAG looks ahead at what 2016 has in store for HPC and finds people, not technology, to be the most important issue. “A disconcertingly large proportion of the software used in computational science and engineering today was written for friendlier and less complex technology. An explosion of attention is needed to drag software into a state where it can effectively deliver science using future HPC platforms.”
The fastest supercomputers are built with the fastest microprocessor chips, which in turn are built upon the fastest switching technology. But, even the best semiconductors are reaching their limits as more is demanded of them. In the closing months of this year, came news of several developments that could break through silicon’s performance barrier and herald an age of smaller, faster, lower-power chips. It is possible that they could be commercially viable in the next few years.
Researchers from Zhejiang University and Hangzhou Dianzi University in China have developed the Darwin Neural Processing Unit (NPU), a neuromorphic hardware co-processor based on Spiking Neural Networks, fabricated by standard CMOS technology. “Its potential applications include intelligent hardware systems, robotics, brain-computer interfaces, and others. Since it uses spikes for information processing and transmission, similar to biological neural networks, it may be suitable for analysis and processing of biological spiking neural signals, and building brain-computer interface systems by interfacing with animal or human brains.”
In this video, Dr. Michael Karasick from IBM moderates a panel discussion on Machine Learning. “The success of cognitive computing will not be measured by Turing tests or a computer’s ability to mimic humans. It will be measured in more practical ways, like return on investment, new market opportunities, diseases cured and lives saved.”