Entries filed under “Network”

HPC-related networking and interconnect news.

Revolutionary Thinking, Evolutionary Technology – How Intel’s Bet on Fabric Integration will Enable Exaflops

In this special guest feature from The Exascale Report, Mike Bernhardt writes that Intel is placing a big bet on fabric integration on its journey to Exascale.

We already know exascale-class systems will be far too expensive to make them commercially available. And we’ve heard several years of discussion on the staggering power requirements an exaFLOPS system would require. So, is anyone doing anything creative to get past these barriers?

With a clever brand most of us marketing types can really appreciate, Intel’s True Scale Fabric represents an architectural change that can potentially benefit Cloud Computing, Big Data, HPC, and establish a path toward exascale.
The architectural change Intel is going for here is to bring the processor and the controller closer together. There’s more to it of course including some specialized hardware and software as one would expect, but the net effect according to Intel will be a reduction of power consumption and the density of the servers.

The move in this direction did not happen overnight. Intel has been working on this strategy for quite some time. Intel’s portfolio of assets to support this integration of storage and network controllers with Intel’s processors has been significantly enhanced with its acquisition of HPC interconnect technology from Cray, the acquisition of the Ethernet switching company, Fulcrum
Microsystems, and pulling in the InfiniBand assets of QLogic.

Joe Yaworski, Intel’s Fabric Product Marketing Manager, recently presented five key points to emphasize Intel’s wisdom in moving in this direction:

  • Datacenter (HPC & Cloud) growth requires new innovations to meet the growing demand and performance requirements
  • Fabrics are becoming the next bottleneck to an unrelenting need for data in cloud and HPC workloads
  • Fabric integration will be required to address the growing need for bandwidth, scalability, power and system density
  • Intel is uniquely positioned with its acquisitions of – Cray interconnect group, QLogic InfiniBand program and products and Fulcrum assets to meet the need with fabrics technology innovation and CPU platform integration in the future
  • One of the solutions for the future may be moving the fabric controller closer to the CPU. This will provide the potential for meeting high bandwidth and performance goals, while at the same time delivering the highest possible energy efficiency

For The Exascale Report, we do not consider this article in the category of a product announcement as any products based on such an integrated fabric are still in the future. We do see this as an important path to be explored, and we will continue to monitor and report on this topic.

Download the PDF or Subscribe to The Exascale Report.

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Video: A Generic Methodology for Optimizing an HPC Storage System

In this video from the HPC Advisory Council Switzerland Conferenc, Zhiqi Tao from Intel (formerly of Whamcloud) presents: A Generic Methodology for Optimizing an HPC Storage System.

Designing a large scale, high performance storage system presents significant challenges. This paper describes a step-by-step approach to designing a storage system and presents a design methodology based on an iterative approach that applies at both the component level and the overall system level. The paper includes a detailed case study in which a Lustre storage system is designed using the approach and methodology presented.

Read the Whamcloud Whitepaper on this topic or Download the Slides (PDF).

In related news, the Lustre User Group conference will take place in San Diego April 16-18.

Also posted in Events, HPC, HPC Advisory Council Workshop, HPC Hardware, HPC Software, Lustre, Storage, Video | Leave a comment

Video: Accelerating Big Data with Hadoop (HDFS, MapReduce and HBase) and Memcached

In this video from the HPC Advisory Council Switzerland Conference, D.K. Panda from Ohio State University presents: Accelerating Big Data with Hadoop (HDFS, MapReduce and HBase) and Memcached. Download the slides (PDF).

Also posted in Events, Hadoop, HPC, HPC Advisory Council Workshop, HPC Hardware, inside-BigData, Video | Leave a comment

Video: Mellanox – The Foundation for Scalable Computing

In this video from the HPC Advisory Council Switzerland Conference, Colin Bridger presents: Mellanox: The Foundation for Scalable Computing.

Download the Slides (PDF).

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Video: Fast Deadlock-Free Routing for InfiniBand Networks

In this video from the HPC Advisory Council Switzerland Conference, Torsten Hoefler from ETH Zurich presents: Fast Deadlock-Free Routing for InfiniBand Networks. Download the slides (PDF).

Also posted in Events, HPC, HPC Advisory Council Workshop, HPC Hardware, Video | Leave a comment

Video: Experiences from the Deployment of TACC’s Stampede System

In this video from the HPC Advisory Council Switzerland Conference, Karl Schulz from the Texas Advanced Computing Center presents: Experiences from the Deployment of TACC’s Stampede System.

Stampede is one of the largest computing systems in the world for open science research. Stampede system components are connected via a fat-tree, FDR InfiniBand interconnect. One hundred and sixty compute racks house compute nodes with dual, eight-core sockets, and feature the new Intel Xeon Phi coprocessors. Additional racks house login, I/O, big-memory, and general hardware management nodes. Each compute node is provisioned with local storage. A high-speed Lustre file system is backed by 76 I/O servers.

Download the slides (PDF).

Also posted in Co-processors, Compute, Events, HPC, HPC Advisory Council Workshop, HPC Hardware, New Installations, Video | Leave a comment

Speed Your Data with Tips from ESnet’s FasterData Site

Over at the Energy Sciences Network, Jon Bashor writes that ESnet’s FasterData.es.net is popular online repository of tips and tricks for improving network performance. Maintained by Brian Tierney for the last 15 years or so, the site comprises around 120 pages, about 50% of the page views where on the pages of that focus on tuning Linux hosts for better network performance on network paths above 1 gigabit per second.

There are a few settings that aren’t defaults and if you use them, they can gain you a lot in terms of performance,” said Tierney, cautioning that the same settings will actually downgrade the performance of slower networks or home routers. “The site contains a lot of arcane details that are hard to memorize, so users can go to a page, copy and paste the settings into their systems.”

Read the Full Story.

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The Villany of Silent Data Corruption

Over at the Emulex Blog, Sonny Singh writes that increasing complexity of data center environments and growth in storage have led to significant concerns about silent data corruption.

But really what it comes down to is without end-to-end protection technology, data corruption can go unnoticed until recovery is difficult and costly or even impossible to perform. Furthermore, without end-to-end integrity checking, these silent data corruptions can lead to unexpected and unexplained problems.

Read the Full Story or check out the podcast on this topic from Radio Free HPC.

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Sponsored Post: OpenFabrics Software Events Coming to Monterey in April

Be a part of the OpenFabrics Alliance’s OpenFabrics Software events in Monterey, CA.

  • The OFA User Workshop, April 18-19, provides opportunities to share experiences and learn from a community of OFS users.
  • The International Developer’s Workshop, April 21-24, will focus on the development and improvement of OFS as well as major developments in RDMA, etc. Agenda and more information is available on OpenFabrics.org.

Registration for the two events is now open. For more details, check out the OFA Newsletter.

Also posted in Events, HPC, HPC Hardware, HPC Software, Open Fabrics, Open Fabrics Workshop, Sponsored Post | Leave a comment

SGI Clears Way to Sell IP or Other Assets

Over at The Register, Timothy Prickett Morgan writes that SGI has rejiggered its credit facility with Wells Fargo Capital Finance ahead of a possible sale of intellectual property or other assets.

SGI CEO Jorge Titinger, who came on board a year ago, has made no secret that the company has been doing a comprehensive review of its assets and intellectual property to gauge its worth and potential items that it might sell. The company did a slew of low-margin deals, many of them in Europe, that saw Mark Barrenechea leave SGI in December 2011. Two months later, after SGI did the math and saw how these deals were not very for the bottom line, the company did yet another restructuring in its long history of such maneuvers, and a few weeks later, Titinger took over and tried to limit the damage that the nine deals, worth $87m, did to the company’s bottom line.

Morgan goes on to speculate that SGI might be looking to license its NUMAlink technolgoy to companies like Nvidia or Cisco. Read the Full Story.

Also posted in Business of HPC, HPC, HPC Hardware | Leave a comment

How Intel’s True Scale QDR-80 IB Scales for Less

Intel has been rather quiet about their True Scale InfiniBand products since they acquired QLogic’s IB technology and engineering teams in January 2012. It’s looking like that is starting to change with a series of interviews at The Register and Semi-Accurate that describe how True Scale QDR-80 products measure up to next-generation FDR offerings from Mellanox. To learn more, I caught up with Intel’s Joe Jaworsky last week and got an update on where Intel is heading with fabrics on its journey to Exascale computing.

If you’ll recall, the True Scale architecture replaces traditional Verbs-based MPI libraries with the Performance Scaled Messaging (PSM) layer. Designed specifically with HPC performance in mind, this approach does not require address lookups, which gives you the goodness of lower latency. In large deployments such as those in the Tri-Labs, True Scale has delivered impressive scalability as described in Sandia’s report entitled: Unprecedented Scalability and Performance of the New NNSA tri-lab Linux Capacity Cluster 2, which is part of the SC12 Proceedings.

The performance gains that Sandia users are experiencing with their applications on the new TLCC2 Chama has resulted in many positive feedbacks from happy users…. As pointed out in the introduction, to the scales we have benchmarked on Chama, we are seeing unprecedented performance and scalability of many key Sandia applications.

So how did Intel get True Scale to scale so well? They use something called QDR-80 to double-up 40Gbps QDR ports, thus delivering 80Gbps. While this is a neat trick in itself, Intel has paired this with lower pricing than FDR alternatives. The net-net of this is that Intel is offering low latency interconnects for less money, a persuasive message indeed for supercomputer buyers who would love to take that extra cash and use it to buy more cores.

Watch this space as Intel continues to beef up its portfolio on its journey to Exascale computing. Compute is just one element of a performing, balanced architecture. As Intel brings fabrics (Cray Aries, True Scale, and Fulcurm) and storage (Lustre expertise and SSDs) to bear, the company is building a formidable platform for the future of HPC.

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Video: LSI and Seneca Power Big Data at PSC

In this video, technologists from the Pittsburgh Supercomputer Center work with LSI and Seneca to deploy high bandwidth SAS solutions for data-intensive computing.

Also posted in HPC, HPC Hardware, Storage, Video | Leave a comment

HP Taps Mellanox for Low Latency Blade Switch

Over at the HP Blog, Steve Barry writes that the days of Blade servers being hampered by the limitations of top-of-rack switches may be over thanks to new technology from Mellanox. Designed specifically for customers that demand performance and raw bandwidth the Mellanox SX1018HP blade switch provides up to sixteen 40Gb server downlinks and up to eighteen 40Gb network uplinks for an amazing 1.3Tb/s of throughput.

For customers currently running Infiniband networks, the appeal of being able to collapse their data requirements onto a single network has always been tempered by the lack of support for Remote Direct Memory Access (RDMA) on Ethernet networks. Again, HP and Mellanox lead the way in blade switches. The SX1018HP supports RDMA over Converged Ethernet (RoCE) allowing those RDMA tuned applications to work across both Infiniband and Ethernet networks. When coupled with the recently announced HP544M 40Gb Ethernet/FDR Infiniband adapter, customers can now support RDMA end to end on either network and begin the migration to a single Ethernet infrastructure.

Read the Full Story.

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How to Passively Monitor Network Round-Trip Times

Over at the Boundary Blog, Steven Strowes writes that understanding network delay is key to understanding some important aspects of your network performance.

This post describes how Boundary uses a well-known TCP mechanism to calculate round-trip times (RTTs) between any two hosts by passively monitoring TCP traffic flows, i.e., without actively launching ICMP echo requests (pings). The post is primarily an overview of this one aspect of TCP monitoring, it also outlines the mechanism we are using, and demonstrates its correctness.

Read the Full Story.

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Fujitsu Develops 32 Gbps Transceivers for Inter-Processor Communications

This week Fujitsu Laboratories announced the development of transceiver circuits capable of communicating at 32 Gbps, a world record. The company said the new technology will support inter-processor communications at roughly twice today’s rates, leading to improved performance in next-generation of servers and supercomputers.

Figure 2: Schematic of transmitter circuit and breakdown of power consumption

Transmitter circuits transmit data from multiple channels that have been multiplexed into a single channel. The final-stage multiplexer not only consumes considerable amount of power, but also will approach the limit of its operating speed as data rates increase. Fujitsu Laboratories has developed a transmitter circuit that eliminates the need for a final-stage multiplex circuit (2-to-1 multiplexer). Rather than using conventional binary values (0, 1) in the transmitted signals, the new circuit uses ternary values (0, 1, 2). This makes it possible to restore the original data on the receiving end using only the existing receiver circuit functionality, without having to add any special circuitry (Figure 2, left). As a result, it exceeds the speed limit of conventional transmitter units. This is also why power consumption can be reduced by roughly 30% compared to the existing technology (Figure 2, right).

Details of the new technologies were presented at the IEEE International Solid-State Circuits Conference 2013 this week in San Francisco. Read the Full Story.

Also posted in Computing Research, HPC, HPC Hardware | Leave a comment

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