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Fujitsu Develops High-Speed Software for Deep Learning

“Fujitsu Laboratories has newly developed parallelization technology to efficiently share data between machines, and applied it to Caffe, an open source deep learning framework widely used around the world. Fujitsu Laboratories evaluated the technology on AlexNet, where it was confirmed to have achieved learning speeds with 16 and 64 GPUs that are 14.7 and 27 times faster, respectively, than a single GPU. These are the world’s fastest processing speeds(2), representing an improvement in learning speeds of 46% for 16 GPUs and 71% for 64 GPUs.”

Radio Free HPC Looks at Machine Learning and Data Locality

Is Machine Learning more of a Data Movement problem than a Processing problem? In this podcast, the Radio Free HPC team looks at use cases for Machine Learning where data locality is critical for performance. “Most of the Machine Learning hearing stories we hear involve a central data repository. Henry says he is not hearing enough about how Machine Learning is going to deal with the problem of massive data streams from things like sensors. Such data, he contends, will have to be processed at the source.”

One Stop Systems Showcases Open Compute Flash Array with 500 TB in 2U

This week at the Flash Memory Summit, One Stop Systems showcased the OCP Flash Storage Array (OCP-FSA), supporting up to 500TB of Flash storage in a 2U form factor. Designed to comply with the Open Rack Standards set by the Open Compute Project, the OCP-FSA is one of the first 500TB Flash Storage Arrays in 2U rack space.

Curtiss-Wright & Dolphin Speed HPEC System Fabric

Today Curtiss-Wright’s Defense Solutions division announced that it is collaborating with Dolphin Interconnect Solutions to bring Dolphin’s eXpressWare PCIe Software Suite to the embedded aerospace and defense market. Available separately or as part of Curtiss-Wright’s OpenHPEC Accelerator Suite of best-in-class software tools, this PCIe Fabric Communications suite speeds and simplifies the design of high-speed, low-latency PCIe fabric-based peer-to-peer communications in OpenVPX-based High Performance Embedded Computing (HPEC) systems for demanding Radar, SIGINT and EW applications.

Raj Hazra Presents: Driving to Exascale

Raj Hazra presented this talk at ISC 2016. “As part of the company’s launch of the Intel Xeon Phi processor, Hazra describes how how cognitive computing and HPC are going to work together. “Intel will introduce and showcase a range of new technologies helping to fuel the path to deeper insight and HPC’s next frontier. Among this year’s new products is the Intel Xeon Phi processor. Intel’s first bootable host processor is specifically designed for highly parallel workloads. It is also the first to integrate both memory and fabric technologies. A bootable x86 CPU, the Intel Xeon Phi processor offers greater scalability and is capable of handling a wider variety of workloads and configurations than accelerator products.”

Record Participation Sets Stage for next NVM Express Plugfest

Today NVM Express, Inc. released the results of its fifth NVM Express (NVMe) Plugfest. The event was a distinct success, with the highest attendance to date. “NVM Express is quickly being adopted as a high performance interface standard for PCIe SSDs, and compatibility among different products is essential for greater market adoption,” said Frank Shu, VP of R&D, Verification Engineering & Compatibility Test at Silicon Motion Inc. “We are proud of having our products successfully pass through the NVMe Plugfest in ensuring compliance to the specification as well as interoperability with other NVMe products.”

University of Maryland and U.S. Army Research Lab to Collaborate on HPC

Today the University of Maryland (UMD) and the U.S. Army Research Laboratory (ARL) announced a strategic partnership to provide HPC resources for use in higher education and research communities. As a result of this synergistic partnership, students, professors, engineers and researchers will have unprecedented access to technologies that enable scientific discovery and innovation.

White House Releases Strategic Plan for NSCI Initiative

This week the White House Office of Science and Technology Policy released the Strategic Plan for the NSCI Initiative. “The NSCI strives to establish and support a collaborative ecosystem in strategic computing that will support scientific discovery and economic drivers for the 21st century, and that will not naturally evolve from current commercial activity,” writes Altaf Carim, William Polk, and Erin Szulman from the OSTP in a blog post.

Video: Andrew Lumsdaine on Computing Trends at PASC16

In this video from PASC16, Andrew Lumsdaine from Indiana University gives his perspectives on the conference. “The PASC16 Conference, co-sponsored by the Association for Computing Machinery (ACM) and the Swiss National Supercomputing Centre (CSCS), brings together research across the areas of computational science, high-performance computing, and various domain sciences.”

Supermicro Now Shipping Intel Xeon Phi Systems with Omni-Path

“With our latest innovations incorporating Intel Xeon Phi processors in a performance and density optimized Twin architecture and 100Gbps OPA switch for high bandwidth connectivity, our customers can accelerate their applications and innovations to address the most complex real world problems.”