“Deep learning developers and researchers want to train neural networks as fast as possible. Right now we are limited by computing performance,” said Dr. Diamos. “The first step in improving performance is to measure it, so we created DeepBench and are opening it up to the deep learning community. We believe that tracking performance on different hardware platforms will help processor designers better optimize their hardware for deep learning applications.”
Oak Ridge National Lab is hosting a 3-day GPU Mini-hackathon led by experts from the OLCF and Nvidia. The event takes place Nov. 1-3 in Knoxville, Tennessee. “General-purpose Graphics Processing Units (GPGPUs) potentially offer exceptionally high memory bandwidth and performance for a wide range of applications. The challenge in utilizing such accelerators has been the difficulty in programming them. This event will introduce you to GPU programming techniques.”
“As more organizations turn to high performance computing to process large data sets, demand is growing for scalable and secure data centre solutions. The source, availability and reliability of the power grid infrastructure is becoming a critical factor in a data centre site selection decision,” said Jeff Monroe, CEO at Verne Global. “Verne Global is able to deliver EI a forward-thinking path for growth with a solution that combines unparalleled costs savings with operational efficiencies to support their data-intensive research.”
Today DDN Japan announced that the University of Tokyo and the Joint Center for Advanced High Performance Computing (JCAHPC) has selected DDN’s burst buffer solution “IME14K” for their new Reedbush supercomputer. “Many problems in science and research today are located at the intersections of HPC and Big Data, and storage and I/O are increasingly important components of any large compute infrastructure.”
In this podcast, the Radio Free HPC team discuss Henry Newman’s recent editorial calling for a self-descriptive data format that will stand the test of time. Henry contends that we seem headed for massive data loss unless we act.
Today Quantum Corp. announced that two of Europe’s premier research institutions are using the company’s StorNext workflow storage as the foundation for managing their growing data and enabling a range of scientific initiatives. “With the StorNext platform, we have removed barriers to research,” Thomas Disper, CISO and Head of IT, Max Planck Institute for Chemistry. “It allows us to provide a lot more capacity quickly and easily. We don’t need to give research teams data limits, and storage for new projects can be ready in an afternoon.”
The National Computational Infrastructure in Canberra, Australia’s national advanced computing facility, is the first Australian institution to deploy the latest generation of Intel Xeon Phi processors, formerly code named Knights Landing. “NCI is leading efforts in the scientific community to tune applications for Intel Xeon Phi processors,” explains Dr Muhammad Atif, NCI’s HPC Systems and Cloud Services Manager. “We have identified a large number of applications that will benefit from this hardware and software paradigm, including those applications in the domains of computational physics, computational chemistry and climate research.”
Maria Chan from NST presented this talk at Argonne Out Loud. “People eagerly anticipate environmental benefits from advances in clean energy technologies, such as advanced batteries for electric cars and thin-film solar cells. Optimizing these technologies for peak performance requires an atomic-level understanding of the designer materials used to make them. But how is that achieved? Maria Chan will explain how computer modeling is used to investigate and even predict how materials behave and change, and how researchers use this information to help improve the materials’ performance. She will also discuss the open questions, challenges, and future strategies for using computation to advance energy materials.”
The European Fortissimo Project has issued its Second Call for Proposals. Fortissimo is a collaborative project that enables European SMEs to be more competitive globally through the use of simulation services running on High Performance Computing Cloud infrastructure.
Today Cadence Design Systems announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing platforms. Working together, Cadence and TSMC have developed some of the first design IP offerings for the 7nm process, offering early IP access to protocols that are optimized for and most relevant to mobile and HPC applications.