In this video from the GPU Technology Conference, Brett Stouder from Seneca describes the company’s new Nexlink A24 Series Server, which Sports Up to 4 Intel Xeon Phi Coprocessors or Nvidia Tesla GPUs in a 2U chassis.
Seneca NexLink A24 Sports Up to 4 Intel Xeon Phi Coprocessors or 4 Nvidia GPUs
Day 3 Keynote from GTC: Behind the Science in Automotive Design
At insideHPC, we are very pleased to bring you live streaming keynotes from the GPU Technology Conference this week in San Jose.
Tune in right here on Thursday, March 21 at 11:00am PT for the next keynote as Ralph Gilles from Chrysler Group LLC presents: Behind the Science in Automotive Design.
Ralph Gilles, senior vice president – Product Design and president and CEO – SRT (Street and Racing Technology) Brand and Motorsports at Chrysler Group LLC and the mind behind some of the company’s most innovative products, will provide a behind-the-scenes look at the auto industry. Gilles will review how GPUs are used to advance every step of the automobile development process – from the initial conceptual designs and engineering phases through product assembly and marketing. He will also discuss and how Chrysler Group utilizes GPUs and the latest technologies to build better, safer cars and reduce time to market.
Revolutionary Thinking, Evolutionary Technology – How Intel’s Bet on Fabric Integration will Enable Exaflops
In this special guest feature from The Exascale Report, Mike Bernhardt writes that Intel is placing a big bet on fabric integration on its journey to Exascale.
We already know exascale-class systems will be far too expensive to make them commercially available. And we’ve heard several years of discussion on the staggering power requirements an exaFLOPS system would require. So, is anyone doing anything creative to get past these barriers?
With a clever brand most of us marketing types can really appreciate, Intel’s True Scale Fabric represents an architectural change that can potentially benefit Cloud Computing, Big Data, HPC, and establish a path toward exascale.
The architectural change Intel is going for here is to bring the processor and the controller closer together. There’s more to it of course including some specialized hardware and software as one would expect, but the net effect according to Intel will be a reduction of power consumption and the density of the servers.
The move in this direction did not happen overnight. Intel has been working on this strategy for quite some time. Intel’s portfolio of assets to support this integration of storage and network controllers with Intel’s processors has been significantly enhanced with its acquisition of HPC interconnect technology from Cray, the acquisition of the Ethernet switching company, Fulcrum
Microsystems, and pulling in the InfiniBand assets of QLogic.
Joe Yaworski, Intel’s Fabric Product Marketing Manager, recently presented five key points to emphasize Intel’s wisdom in moving in this direction:
- Datacenter (HPC & Cloud) growth requires new innovations to meet the growing demand and performance requirements
- Fabrics are becoming the next bottleneck to an unrelenting need for data in cloud and HPC workloads
- Fabric integration will be required to address the growing need for bandwidth, scalability, power and system density
- Intel is uniquely positioned with its acquisitions of – Cray interconnect group, QLogic InfiniBand program and products and Fulcrum assets to meet the need with fabrics technology innovation and CPU platform integration in the future
- One of the solutions for the future may be moving the fabric controller closer to the CPU. This will provide the potential for meeting high bandwidth and performance goals, while at the same time delivering the highest possible energy efficiency
For The Exascale Report, we do not consider this article in the category of a product announcement as any products based on such an integrated fabric are still in the future. We do see this as an important path to be explored, and we will continue to monitor and report on this topic.
Download the PDF or Subscribe to The Exascale Report.
Video: Dell’s Modular HPC – Exascale Block by Block
In this video from the HPC Advisory Council Switzerland Workshop, Kris Buggenhout from Dell presents: Modular HPC, Exascale Block by Block.
Nvidia to Stack DRAM on Future ‘Volta’ GPUs
Over at The Register, Timothy Prickett Morgan writes that Nvidia has announced plans to stack up DRAM on future ‘Volta’ GPUs to deliver over 1TB/sec of memory bandwidth. Due sometime around 2016, Volta’s memory technology will bring memory closer to the GPU, increasing bandwidth while reducing latency.
Volta is going to solve one of the biggest issues with GPUs today, which is access to memory bandwidth,” explained Huang. “The memory bandwidth on a GPU is already several times that of a CPU, but we never seem to have enough.” So with Volta, Nvidia is going to get the memory closer to the GPU so signals do not have to come out of the GPU, onto a circuit board, and into the GDDR memory. This current approach takes more power (you have to pump up the signal to make it travel over the board), introduces latencies, decreases bandwidth.
In related projects, Micron, Intel, and IBM are partnering on an effort to stack up DRAM, with hopes to commercialize something in the next few years. Read the Full Story.
Video: A Generic Methodology for Optimizing an HPC Storage System
In this video from the HPC Advisory Council Switzerland Conferenc, Zhiqi Tao from Intel (formerly of Whamcloud) presents: A Generic Methodology for Optimizing an HPC Storage System.
Designing a large scale, high performance storage system presents significant challenges. This paper describes a step-by-step approach to designing a storage system and presents a design methodology based on an iterative approach that applies at both the component level and the overall system level. The paper includes a detailed case study in which a Lustre storage system is designed using the approach and methodology presented.
Read the Whamcloud Whitepaper on this topic or Download the Slides (PDF).
In related news, the Lustre User Group conference will take place in San Diego April 16-18.
Record Simulations Conducted on Lawrence Livermore Supercomputer
Over at Lawrence Livermore, Breanna Bishop writes that researchers at LLNL have performed record simulations using all 1,572,864 cores of the Sequoia supercomputer. As the first supercomputer to exceed one million computational cores, Sequoia is also is No. 2 on the TOP500 with 16.3 petaflops of performance.
SIRIS simulation on Sequoia of the interaction of a fast-ignition-scale laser with a dense DT plasma.
The simulations were performed by Frederico Fiuza, a physicist and Lawrence Fellow at LLNL. Designed to study the interaction of ultra-powerful lasers with dense plasmas in a proposed method to produce fusion energy, the project is part of the U.S. Department of Energy’s Office of Fusion Energy Science Program.
Using the OSIRIS code, Fiuza demonstrated excellent scaling in parallel performance to the full 1.6 million cores of Sequoia. By increasing the number of cores for a relatively small problem of fixed size, what computer scientists call “strong scaling,” OSIRIS obtained 75 percent efficiency on the full machine. But when the total problem size was increased, what is called “weak scaling,” a 97 percent efficiency was achieved.
This means that a simulation that would take an entire year to perform on a medium-size cluster of 4,000 cores can be performed in a single day. Alternatively, problems 400 times greater in size can be simulated in the same amount of time,” Fiuza said. “The combination of this unique supercomputer and this highly efficient and scalable code is allowing for transformative research.”
Read the Full Story.
Video: Accelerated Computing Goes Beyond HPC to Tackle Big Data
In this video, Sumit Gupta from Nvidia presents: Accelerated Computing Goes Beyond HPC. A wide array of companies are now using GPUs to accelerate Big Data analytics, and Gupta describes how these efforts are delivering competitive advantage.
New Penguin Relion 2808GT Delivers Leading Compute Density for HPC Apps
Today Penguin Computing announced the availability of the Relion 2808GT, a high-density server platform that supports eight GPUs or coprocessors in only 2U. Designed for scientific and engineering applications, the Relion 2808GT is tailor made for popular codes such as Matlab, Amber and Abaqus.
Penguin has been delivering integrated GPU computing clusters since the version 1.0 of this technology,” said CEO Charles Wuischpard. “The new Relion 2808GT platform in conjunction with the latest GPU and coprocessor technology delivers unprecedented levels of performance. The Relion 2808GT enables our HPC customers to further accelerate their research by shortening the time to result for their simulations.”
In terms of computational density, a fully configured server with eight NVidia K20 GPUs can achieve 28 TFLOPs of single precision floating point performance.
The Relion 2808GT will be displayed at the NVidia GPU Technology Conference from March 18 – 21 in San Jose, California. Read the Full Story.
Tuesday Keynote from GPU Technology Conference
In this video, Nvidia’s CEO Jen-Hsun Huang kicks off the GTC Conference with a talk on What’s Next in GPU Technology.
Short on time? In this video, we’ve grabbed the HPC section of the keynote for your viewing pleasure.
At insideHPC, we are very pleased to bring you live streaming keynotes from the GPU Technology Conference all this week from San Jose. Tune in right here on Wednesday, March 20 at 11:00am PT for the next keynote from Erez Lieberman Aiden from the Baylor College of Medicine.
Video: KernelGen — Next-generation Compiler Platform for Accelerating GPUs
In this video from the HPC Advisory Council Switzerland Conference, Dmitry Mikushin from the University of Lugano presents KernelGen — Next-generation Compiler Platform for Accelerating GPUs. Download the Slides (PDF).
Video: GPU Computing With Nvidia’s Kepler Architecture
In this video from the HPC Advisory Council Switzerland Conference, Axel Koehler from Nvidia presents: GPU Computing With Nvidia’s Kepler Architecture.
Download the Slides (PDF). You can also see Kohler’s other talk from last week on Management of Large-scale GPU Clusters.
In related news, be sure to tune in to insideHPC tomorrow for an exclusive, live-streamed keynote from the GPU Technology Conference, starting at 9:00am PT, Tuesday, March 19. Nvidia CEO Jen-Hsun Huang will present What’s Next in GPU Technology.
Direct MPI from NVIDIA Tesla and Intel Xeon Phi Accelerator Memories on an IB Cluster
In this video from the HPC Advisory Council Switzerland Conference, Sadaf Alam from the Swiss Supercomputing Center presents: Direct MPI from NVIDIA Tesla and Intel Xeon Phi Accelerator Memories on an InfiniBand Cluster.
Heterogeneous Computing for Dummies
Over at the AccelerEyes Blog, John Melonakos writes that the next 10 years of HPC will be defined by heterogeneous computing.
In terms of sheer capacity to crunch numbers, GPUs can crunch more numbers per minute than CPUs. They have thousands of cores for number crunching. They are more powerful. They also use less energy per computation than CPUs. Note that a GPU core is not nearly as capable as a CPU core in terms of the kinds of things they can do, but there are many more of them available.
Read the Full Story.
Video: Accelerating Big Data with Hadoop (HDFS, MapReduce and HBase) and Memcached
In this video from the HPC Advisory Council Switzerland Conference, D.K. Panda from Ohio State University presents: Accelerating Big Data with Hadoop (HDFS, MapReduce and HBase) and Memcached. Download the slides (PDF).
