The Embree kernel approach, using the Intel Xeon Phi coprocessor is applicable to many situations. The implementation can be tuned to the hardware available, using different vector widths and workloads per ray. With a flexible toolkit for rendering, applications can take advantage of the latest hardware acceleration to achieve maximum performance.
In this special guest feature, Tom Wilkie from Scientific Computing World writes that software approaches to energy efficiency in HPC may yield unexpected improvements in the hardware of next-generation mobile phone networks. “Adept, a European research project addressing the energy-efficient use of parallel technologies, is expected to release a set of benchmarks that it has developed to characterize the energy consumption of programming models on different architectures.”
“These new flash products greatly expand the range of our total product portfolio and demonstrate how Seagate’s acquisition of the LSI flash technologies is paying off. The Nytro XF1440/XM1440 SSDs deliver the highest performance in the smallest power envelope. The XP6500 flash accelerator card provides ultra-low latency capability for applications that require fast logging and produce significantly higher transactions per second,–something today’s applications demand.”
As reported here, President Obama established the National Strategic Computing Initiative (NSCI) in July to ensure the United States continues leading high performance computing over the coming decades. Today, IDC announced what promises to be the first NSCI discussion involving the lead agencies at their next HPC User Forum.
In this video from the ISC 2015 conference, Erich Strohmaier from NERSC and Jack Dongarra from University of Tennessee discuss the latest HPC trends reflected in the 45th TOP500 list. “Nine systems in the top 10 were installed in 2011 or 2012, and this low level of turnover among the top supercomputers reflects a slowing trend that began in 2008.”