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Video: Teens Apply HPC at SDSC Summer Program

rehs-group

In this video, student participants in Research Experience for High School Students (REHS) program discuss their experiences using HPC resources at the San Diego Supercomputer Center at UC San Diego (SDSC).

Advancing HPC with Collaboration & Co-design

UCX

In this special guest feature from Scientific Computing World, Tom Wilkie reports on two US initiatives for future supercomputers, announced at the ISC in Frankfurt in July.

Introducing the Intel Modern Code Community

Scott Apeland, Director, Intel Developer Program

“Building on the success of the Intel Parallel Computing Centers, Intel is announcing the Intel Modern Code Developer Community to help HPC developers to code for maximum performance on current and future hardware. Targeting over 400,000 HPC-focused developers and partners, the program brings tools, training, knowledge and support to developers worldwide by offering access to a network of elite experts in parallelism and HPC. The broader developer community can now gain the skills needed to unlock the full potential of Intel hardware and enable the next decade of discovery.”

Job of the Week: Director of Sales at Ryft

ryft

Ryft in San Francisco is seeking a Director of Sales in our Job of the Week.

Video: HPC Workloads using Docker

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In this video from ISC 2015, Wolfgang Gentzsch from The UberCloud presents: HPC Workloads Using Docker. “The UberCloud Project provides an environment to run HPC workloads on a variety of cloud providers. Wolfgang elaborates on the projects and provides his experience about the roadblocks towards a more flexible cloud-backed HPC future.”

Agenda Posted for HPC User Forum, Sept. 8-10 in Broomfield

Steve Conway and Earl Joseph of IDC

IDC has published the agenda for their next HPC User Forum. The event will take place Sept. 8-10 in Broomfield, CO.

Nested Parallelism

phi-compressor

The benefits of nested parallelism on highly threaded applications can be determined and quantified. With the number of cores in both the host CPU (Intel Xeon) and the coprocessor (Intel Xeon Phi) continues to increase, much thought must be given to minimizing the thread overhead when many threads need to be synchronized, as well as the memory access for each processor (core). Tasks that can be spread across an entire system to exploit the algorithm’s parallelism, should be mapped to the NUMA node to make them more efficient.

Video: Argonne Presents HPC Plans at ISC 2015

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“In April 2015, the U.S. Department of Energy announced a $200 million supercomputing investment coming to Argonne National Laboratory. As the third of three Coral supercomputer procurements, the deal will comprise an 8.5 Petaflop “Theta” system based on Knights Landing in 2016 and a much larger 180 Petaflop “Aurora” supercomputer in 2018. Intel will be the prime contractor on the deal, with sub-contractor Cray building the actual supercomputers.”

Should Users Reset Performance Expectations for Exascale?

exascale

“Exascale computers are going to deliver only one or two per cent of their theoretical peak performance when they run real applications; and both the people paying for, and the people using, such machines need to have realistic expectations about just how low a percentage of the peak performance they will obtain.”

Intel’s Raj Hazra on the Convergence of HPC & Big Data at ISC 2015

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In this video from ISC 2015, Intel’s Raj Hazra explores how new innovations and Intel’s Scalable System Framework approach can maximize the potential in the new HPC era. Raj also shares details of upcoming Intel technologies, products and ecosystem collaborations that are powering these breakthroughs and ensuring technical computing continues to fulfill its potential as a scientific and industrial tool for discovery and innovation.