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Video: Optimizing Applications for the CORI Supercomputer at NERSC

In this video from SC15, NERSC shares its experience on optimizing applications to run on the new Intel Xeon Phi processors (code name Knights Landing) that will empower the Cori supercomputer by the summer of 2016. “A key goal of the Cori Phase 1 system is to support the increasingly data-intensive computing needs of NERSC users. Toward this end, Phase 1 of Cori will feature more than 1,400 Intel Haswell compute nodes, each with 128 gigabytes of memory per node. The system will provide about the same sustained application performance as NERSC’s Hopper system, which will be retired later this year. The Cori interconnect will have a dragonfly topology based on the Aries interconnect, identical to NERSC’s Edison system.”

Share Your HPC Code in the PRACE CodeVault

Today the European PRACE infrastructure announced the PRACE CodeVault, an open repository containing various high performance computing code samples for the HPC community. The CodeVault is an open platform that supports self-education of learning HPC programming skills where HPC users can share example code snippets, proof-of-concept codes and more.

AWS to Aquire Italy’s NICE Software

Today NICE software in Italy announced that the company is to be acquired by Amazon Web Services, the world’s most comprehensive and broadly adopted cloud platform. With its remote visualization platform, NICE delivers comprehensive Grid & Cloud Solutions for increasing user productivity to access applications and computing resources.

Call for Papers: International Workshop on Performance-Portable Programming Models for Accelerators

The first annual International Workshop on Performance Portable Programming Models for Accelerators has issued its Call for Papers. Known as P^3MA, the workshop will provide a forum for bringing together researchers, vendors, users and developers to brainstorm aspects of heterogeneous computing and its various tools and techniques.

Creating an Exascale Ecosystem Under the NSCI Banner

“We expect NCSI to run for the next two decades. It’s a bit audacious to start a 20 year project in the last 18 months of an administration, but one of the things that gives us momentum is that we are not starting from a clean sheet of paper. There are many government agencies already involved and what we’re really doing is increasing their coordination and collaboration. Also we will be working very hard over the next 18 months to build momentum and establish new working relationships with academia and industry.”

MultiLevel Parallelism with Intel Xeon Phi

“The combination of using both MPI and OpenMP is a topic that has been explored by many developers in order to determine the most optimum solution. Whether to use OpenMP for outer loops and MPI within, or by creating separate MPI processes and using OpenMP within can lead to various levels of performance. In most cases of determining which method will yield the best results will involve a deep understanding of the application, and not just rearranging directives.”

Second Intel Parallel Computing Center Opens at SDSC

Intel has opened a second parallel computing center at the San Diego Supercomputer Center (SDSC), at the University of California, San Diego. The focus of this new engagement is on earthquake research, including detailed computer simulations of major seismic activity that can be used to better inform and assist disaster recovery and relief efforts.

ExaNeSt European Consortium to Develop Exascale Architecture

In this special guest feature, Robert Roe from Scientific Computing World reports that a new Exascale computing architecture using ARM processors is being developed by a European consortium of hardware and software providers, research centers, and industry partners. Funded by the European Union’s Horizon2020 research program, a full prototype of the new system is expected to be ready by 2018.

Video: Theta & Aurora – Big Systems for Big Science

“Aurora’s revolutionary architecture features Intel’s HPC scalable system framework and 2nd generation Intel Omni-Path Fabric. The system will have a combined total of over 8 Petabytes of on package high bandwidth memory and persistent memory, connected and communicating via a high-performance system fabric to achieve landmark throughput. The nodes will be linked to a dedicated burst buffer and a high-performance parallel storage solution. A second system, named Theta, will be delivered in 2016. Theta will be based on Intel’s second-generation Xeon Phi processor and will serve as an early production system for the ALCF.”

New CFD and Geometry Interfaces in Pointwise Meshing Software

Today Pointwise announced the latest release of its meshing software featuring updated native interfaces to computational fluid dynamics (CFD) and geometry codes. Pointwise Version 17.3 R5 also includes geometry import and export to the native file format of Pointwise’s geometry kernel and a variety of bug fixes.