The first annual International Workshop on Performance Portable Programming Models for Accelerators has issued its Call for Papers. Known as P^3MA, the workshop will provide a forum for bringing together researchers, vendors, users and developers to brainstorm aspects of heterogeneous computing and its various tools and techniques.
Intel has opened a second parallel computing center at the San Diego Supercomputer Center (SDSC), at the University of California, San Diego. The focus of this new engagement is on earthquake research, including detailed computer simulations of major seismic activity that can be used to better inform and assist disaster recovery and relief efforts.
Registration is now open for the inaugural Nimbix Developer Summit. With an impressive lineup of speakers & sponsors from Mellanox, migenius, Xilinx, and more, the event takes place March 15 in Dallas, Texas. “The summit agenda will feature topics such as hardware acceleration, coprocessing, photorealistic rendering, bioinformatics, and high performance analytics. The sessions will conclude with a panel of developers discussing how to overcome challenges of creating and optimizing cloud-based applications.”
Today the European Consortium announced a step towards Exascale computing with the ExaNeSt project. Funded by the Horizon 2020 initiative, ExaNeSt plans to build its first straw man prototype in 2016. The Consortium consists of twelve partners, each of which has expertise in a core technology needed for innovation to reach Exascale. ExaNeSt takes the sensible, integrated approach of co-designing the hardware and software, enabling the prototype to run real-life evaluations, facilitating its scalability and maturity into this decade and beyond.
Today Bright Computing announced that Italy-based Do IT Systems has signed up to the Bright Partner Program. “Together, Bright Computing and Do IT Systems offer a compelling proposition for Italian customers that require high quality HPC solutions and remote HPC management,” said Roberto Strano, Technical Manager at Do IT Systems. “We have been very impressed with the Bright software, and we are confident that it will enable our customers to develop and manage HPC clusters in an affordable and efficient way.”
Today Allinea announced that Oak Ridge National Laboratory has deployed its code performance profiler Allinea MAP in strength on the Titan supercomputer. Allinea MAP enables developers of software for supercomputers of all sizes to produce faster code. Its deployment on Titan will help to use the system’s 299,008 CPU cores and 18,688 GPUs more efficiently. Software teams at Oak Ridge are also preparing for the arrival of the next generation supercomputer, the Summit pre-Exascale system – which will be capable of over 150 PetaFLOPS in 2018.
In this video from the Intel HPC Developer Conference at SC15, Kevin O’Leary from Intel presents: Vectorization Advisor in Action for Computer-Aided Formulation. “The talk will focus on a step-by-step walkthrough of optimizations for an industry code by using the new Vectorization Advisor (as part of Intel® Advisor XE 2016). Using this tool, HPC experts at UK Daresbury Lab were able to spot new SIMD modernization and optimization opportunities in the DL_MESO application – an industry engine currently used by “computer-aided formulation” companies like Unilever.”
Lawrence Livermore National Lab is seeking an HPC Compiler & Tools Engineer in our Job of the Week. “As a member of the Development Environment Group in the Livermore Computing (LC) supercomputing center, will work as a software developer specializing in compilers and application development tools for supporting High Performance Computing (HPC). Will work with scientific computing teams, the open source software community, and HPC vendor partners on the development of enabling technologies for the state-of-the-art platforms currently in use and under procurement.”
Today Allinea reports that developers of Roxar Software Solutions at Emerson Process Management used the Allinea Forge to increase the performance of their Tempest MORE next-generation reservoir simulator by 30 percent.
“The path to Exascale computing is clearly paved with Co-Design architecture. By using a Co-Design approach, the network infrastructure becomes more intelligent, which reduces the overhead on the CPU and streamlines the process of passing data throughout the network. A smart network is the only way that HPC data centers can deal with the massive demands to scale, to deliver constant performance improvements, and to handle exponential data growth.”