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SELinux at Lockheed: A New Multi-Level Security Initiative

Sarah Storms, Project Engineer, Lockheed Martin

“Historically cyber security in HPC has been limited to detecting intrusions rather than designing security from the beginning in a holistic, layered approach to protect the system. SELinux has provided the needed framework to address cyber security issues for a decade, but the lack of an HPC and data analysis eco-system based on SELinux and the perception that the resulting configuration is “hard” to use has prevented SELinux configurations from being widely accepted. This presentation will discuss the eco-system that has been developed and certified, debunk the “hard” perception, and illustrate approaches for both government and commercial applications.”

Video: Communication Frameworks for HPC and Big Data

DK Panda, Ohio State University

“This talk will focus on programming models and their designs for upcoming exascale systems with millions of processors and accelerators. Current status and future trends of MPI and PGAS (UPC and OpenSHMEM) programming models will be presented. We will discuss challenges in designing runtime environments for these programming models by taking into account support for multi-core, high-performance networks, GPGPUs, Intel MIC, scalable collectives (multi-core-aware, topology-aware, and power-aware), non-blocking collectives using Offload framework, one-sided RMA operations, schemes and architectures for fault-tolerance/fault-resilience.”

Oak Ridge to Run ParallWare on Titan


Today Oak Ridge announced approval of a project run ParallelWare from Appentra on the Titan Supercomputer. The project includes an allocation of 50,000 core hours on supercomputer. “ParallelWare is an source-to-source parallelizing compiler for sequential scientific programs. ParallelWare automatically discovers the parallelism available int he input sequential C code, and automatically generates parallel-equivalent C code annotated with OpenMP compiler directives.

Bright Computing Collaborates on OpenHPEC Accelerator Suite


Today Curtiss-Wright Corporation announced that its Defense Solutions division is collaborating with leading High Performance Computing software vendor Bright Computing to bring its supercomputing software tools to the embedded Aerospace & Defense market as part of Curtiss-Wright’s recently announced OpenHPEC Accelerator Suite of best-in-class software development tools.

Satoshi Matsuoka to Keynote Workshop on Directives and Tools for Accelerators

Dr. Satoshi Matsuoka, University of Tokyo

The Center for Advanced Computing systems has announced their agenda for the Directives and Tools for Accelerators Workshop. Also known as the Seismic Programming Shift Workshop, the event takes place Oct. 11-13 at the University of Houston.

Allinea Forge Sparks Convergent Science Combustion Simulation


Convergent Science reports that the company has adopted the Allinea Forge development tool suite. As the leader in internal combustion engine (ICE) simulation, Convergent Science is using Allinea to increase the capability and performance of the company’s CONVERGE software.

Presentations Posted from MUG’15 – MVAPICH User Group


Ohio State University has posted presentations from MUG’15 MVAPICH User Group. The event took place Aug. 19-21 in Columbus, Ohio.

Intel HPC Developer Conference Coming to SC15


The first annual Intel HPC Developer Conference is coming to Austin Nov. 14-15 in conjunction with SC15. “The Intel® HPC Developer Conference will bring together developers from around the world to discuss code modernization in high performance computing. Learn what’s next in HPC, its technologies, and its impact on tomorrow’s innovations. Find the solutions to your biggest challenges at the Intel® HPC Developer Conference.”

Best Practices for Maximizing GPU Resources in HPC Clusters

logos nivida bright computing

HPC developers want to write code and create new applications. The advanced nature of HPC often requires that this process be associated with specific hardware and software environment present on a given HPC resource. Developers want to extract the maximum performance from HPC hardware and at the same time not get mired down in the complexities of software tool chains and dependencies.

Video: Debugging HPC Applications at Massive Scales


In this video, LLNL scientists discuss the challenges of debugging programs at scale on the Sequoia supercomputer, which has 1.6 million processors. “Bugs in parallel HPC applications are difficult to debug because errors propagate among compute nodes, programmers must debug thousands of nodes or more, and bugs might manifest only at large scale.”