Entries filed under “HPC”

News and announcements in technologies related to HPC.

Webinar: NSF Big Data Solicitation May 21

On May 21, The National Science Foundation and the National Institutes of Health will host a webinar on their joint Core Techniques and Technologies for Advancing Big Data Science & Engineering solicitation. This webinar is designed to describe the goals and focus of the BIGDATA solicitation, help investigators understand its scope, and answer any questions potential Principal Investigators may have.

The BIGDATA solicitation aims to advance the core scientific and technological means of managing, analyzing, visualizing, and extracting useful information from large, diverse, distributed and heterogeneous data sets so as to: accelerate the progress of scientific discovery and innovation; lead to new fields of inquiry that would not otherwise be possible; encourage the development of new data analytic tools and algorithms; facilitate scalable, accessible, and sustainable data infrastructure; increase understanding of human and social processes and interactions; and promote economic growth and improved health and quality of life.

Update: The webinar audio is now available for replay. Download the slides (PDF).

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Interview: Author Rob Farber on the Secret Sauce for Programmers in the Kepler GPU

In this video, Rob Farber discusses new features in the Nvidia Kepler GPUs that make it easier for programmers to maximize application performance. Recorded at GTC 2012 in San Jose.

Farber’s book, CUDA Application Design and Development was the best-selling title at SC11 and at GTC 2012 this year. The book is designed to meet the needs of working software developers who need to understand GPU programming with CUDA and increase efficiency in their projects.

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New Whitepaper: NVIDIA’s Next-Gen CUDA Compute Architecture – Kepler GK110

If you still looking for more details on the new Kepler GPUs, Nvidia has stepped up with a new GK110 Architecture whitepaper for you.

Comprising 7.1 billion transistors, Kepler GK110 is not only the fastest, but also the most architecturally complex microprocessor ever built. Adding many new innovative features focused on compute performance, GK110 was designed to be a parallel processing powerhouse for Tesla and the HPC market. Kepler GK110 will provide over 1 TFlop of double precision throughput with greater than 80% DGEMM efficiency versus 60‐65% on the prior Fermi architecture. In addition to greatly improved performance, the Kepler architecture offers a huge leap forward in power efficiency, delivering up to 3x the performance per watt of Fermi.  

Is the news all good? Blogger Paul Caheny writes that the K10 in particular continues a disturbing downward trend on memory capacity per FLOPs.

A couple of high level observations on how this fits into general HPC architecture trends. Firstly the ratio of memory capacity and memory bandwidth to compute is likely to continue to decrease, signifying the increasing necessity to make use of strong scaling in applications rather than the previously rich seam of weak scaling. K10 represents a more than 60% fall in Bytes/FLOPs (memory capacity per FLOPs) compared to M2090 and a reduction of 50% in Bytes/sec/FLOPs (memory bandwidth per FLOPs) compared to M2090 (both using SP FLOPs as per K10′s target market). It will be interesting to see what the corresponding numbers are for the upcoming K20.

Download the whitepaper (PDF).

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SGI Brings Kepler K10 GPU to Rackable Servers, K20 in the Fall

In this video, Bill Mannel from SGI describes the company’s GPU-powered HPC solutions. Recorded at GTC 2012 in San Jose.

SGI recently announced announced the availability of a complete, managed GPU solution of its SGI Rackable servers with the new high-performance Nvidia Tesla K10 GPU Computing Accelerator. Coupled with SGI Management and Performance Suite software, the solution is built, completely integrated, and tested in SGI’s manufacturing facility so that it can be installed at the customer site and begin running application codes in less than a day.

Read the Full Story.

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IDC Breakfast Briefing at ISC’12 on June 18

IDC will host its annual Analyst Briefing and Breakfast at ISC’12 on June 18 in Hamburg. You can join IDC’s Earl Joseph, Steve Conway, and Chirag Dekate as they present their expert insight and analysis on the evolving HPC market. This session will examine the drivers and inhibitors impacting the HPC Technical Server market and provide IDC’s latest forecasts.

The event starts at 8:00am in the CCH-Congress Center Hamburg (Hall B). Register now.

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GPUs Power Penguin Computing, from HPC to Cloud and on to the Enterprise

In this video, Tom Coull from Penguin Computing describes the company’s GPU-powered computing solutions for HPC. Penguin On Demand has offered GPUs in the Cloud for years, and the recent Kepler GPU announcement from Nvidia is figuring prominently in Penguin’s plans.

Coulll also describes Penguin Computing’s move to provide enterprise customers with the same powerful server and storage solutions that have powered its HPC customers.

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End-users Need to Design Exascale Computers

 

It’s not size that counts but what you do with your supercomputer, delegates to the GPU Technology Conference in San Jose were told on 16 May.

End-user scientists and engineers need to get involved from the outset in the design of the next generation of machines – expected to be capable of delivering performance in the Exaflop range by the end of this decade – if they want the machines to produce useful scientific and engineering results.

Historically too much emphasis has been put on supercomputer hardware and not enough attention paid to the application software that would run on the machines to produce the results that scientists and engineers want. So during a session on ‘Exascaling your apps’, Steve Scott, the chief technology officer of Nvidia, which organised the conference, warned that if exascale machines were to have a broad impact: ‘We need a wake-up call.’ He did not think that system software would be an issue in the Exascale domain but rather: ‘I’m worried about application software.’

At present, no-one quite knows what the hardware will be for a successful Ex scale machine and this opens up an unprecedented opportunity for end users to get involved in ‘co-design’, Satoshi Matsuoka of the Tokyo Institute of Technology told the session. ‘Co-design will be the big key,’ he said. Because the architectures of the processors and the systems for Exascale computing are not yet fixed, he said, co-design is needed to reflect the needs of the end-user applications in the architectures themselves, right from the outset.

He pointed out that even at the Petaflop level, ‘It has been a challenge to run efficient applications. Scaling up has been a challenge because of the transition to many core and heterogeneous architectures.’ Steve Scott endorsed the point saying that although today’s applications will run on a future Exaflop machine: ‘Will they run well? No!’

The US Department of Energy has already set up three co-design initiatives, according to Jeff Vetter of Oak Ridge National Laboratory. They will be focusing on the areas of Combustion, Materials Science, and Nuclear Power. ‘In the past, the applications teams have been tossed new architectures and told to get on with it,’ he said. Now, in contrast, designers have to tell the users early on what the possibilities might be.

This story originally appeared on HPC Projects. It appears here as part of a cross-publishing agreement with Scientific Computing World.

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GPUs Power Part-Time Scientists’ Plan for Lunar Rover Autonomy

Today at the GTC 2012 conference, a team calling themselves the Part-Time Scientists presented plans for their GPU-powered lunar rover entry in the Google Lunar X Prize.

The autonomous navigation system of Asimov is a major technological leap. While the Russian Moon rovers Lunokhod 1 and 2 in the early 70s were fully controlled from Earth, today’s Mars rovers like NASA’s Mars Exploration Rover “Opportunity”, which has been tirelessly exploring the Red Planet since 2004, are autonomous. However, Opportunity requires nearly three minutes to process a pair of images – a delay that causes it to move at an average speed of just 1 cm/sec or less. New developments by the technology partnership between the DLR Institute of Robotics and Mechatronics (RMC) and the PTS have created, for the first time, an autonomous navigation system for a rover that has the capacity to process multiple images per second. The technology boosts a stereo camera that Asimov will use to calculate its own motion, generate a 2.5-dimensional environmental model, evaluate the site and determine a collision-free path – all in real time.

Read the Full Story.

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Massively Parallel Simulation Counters Antibiotic Resistance

A solution to the problem of antibiotic-resistant bacteria may be closer, as a result of a computer science project to investigate ways of making legacy software run efficiently on heterogeneous systems, the Nvidia GPU Technology Conference was told on 16 May.

Simon McIntosh-Smith, of the University of Bristol in the UK, presented results from a project that ported a very large molecular modelling program to systems with a mix of conventional CPUs and also GPUs. One early result has been the identification of around ten small molecules that could block the biological pathway that creates antibiotic resistance in bacteria. So confident are the researchers in their predictions that the candidate drug molecules are now being synthesised in the laboratory.

Typically, biomolecules such as proteins can be made up from between a thousand and two thousand atoms, whereas the docking molecules, the ligands, will be an order of magnitude smaller – about 50 to 100 atoms. The software is BUDE – the Bristol University Docking Engine – is used to predict the structure of small molecules that can bind tightly to the active sites in large biological molecules. It processes tens of millions of candidate ligands and uses a genetic algorithm-like methodology to select those that bind most tightly, using energy minimisation calculations. It is, said McIntosh-Smith, a very large piece of code, in the region of hundreds of thousands of lines of Fortran. However, only a few thousand lines needed to be ported across to GPU processors.

Because the ten million or so ligands all come in slightly different flavours – they have flexible side chains, for example – the project represents “an embarrassment of parallelism,” he continued. “When we get down to one molecule, we want to test it in many different positions and rotations, so we have even more parallelism.”

Only two results are outside the desirable bounds, so ‘we are now getting very accurate simulation results,’ McIntosh-Smith said. By porting the code across to a heterogeneous CPU+GPU system, he reported a factor of 20 increase in the speed of computation and a factor of 10 improvement in energy efficiency.

The simulation to try to find ligands that would block recently emerged antibiotic-resistance in a bacterium found in Asia took four days and surveyed more than 8 million candidate molecules. Once, he pointed out, it would have taken the biggest and fastest supercomputers in the world to do the calculation, which can now be done by a university research group.

This story originally appeared on HPC Projects. It appears here as part of a cross-publishing agreement with Scientific Computing World.

Also posted in Computing Research, GPUs, HPC Hardware | Leave a comment

Kenya’s First Home-Grown Supercomputer

Mbugua Njihia writes that a team of developers with financial backing from Google are working on Kenya’s first locally assembled supercomputer. And while the project has been underway for a while now, the potential benefits of HPC for the region are just beginning to sink in.

High performance computing can make money by doing the heavy lifting and thereby improving efficiencies across all sectors of the economy and this initiative will be one to keep an eye on; the spin-offs may just prove to be interesting.”

Read the Full Story.

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GPU Proliferation in HPC Reflected in SC Conference Showfloor

Our GTC 2012 coverage continues with Dan Olds’s report on the rapid spread of Cuda and GPU computing. One measure is its increased presence the annual Supercomputing Conference series.

This story is perhaps best told via pictures. In this first picture, we’re looking at the booth layout of the SC07 show floor in Reno. Like a typical SC show, there were a few hundred exhibitors ranging from hardware, software, and service vendors to academic institutions, research labs, and government research organizations. The sole presence of hybrid computing is the tiny green dot at the upper left of the schematic. It’s NVIDIA’s small booth – the lone beachhead for GPU-accelerated HPC. Fast-forward four years and… look at the progress. The SC11 show floor diagram is literally covered with green squares and rectangles.”

Read the Full Story.

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DoD HPC Mod to Double Compute Capacity with Four Petaflop Upgrade

The Department of Defense High Performance Computing Modernization Program (DOD HPCMP) has just completed its largest one-time investment in supercomputing capability supporting the science, engineering, test and acquisition communities of the DoD. The total acquisition is valued at $105 million, and includes $80 million for multiple systems along with an additional $25 million in hardware and software maintenance services. This will more than double the DOD HPCMP’s current sustained computing capability.

This latest acquisition will provide significant capability for DOD scientists and engineers to stretch the boundaries of scientific discovery, expand engineering capabilities and accelerate the delivery of new technologies to the defense communities,” observed John West, director of the HPCMP. The purchase includes seven systems that will collectively provide over 225,000 cores, over 520 gigabytes of memory and a total storage capacity of 23 petabytes. Each system is scheduled to be fully accepted and operational by the end of the calendar year.

The HPC vendors participating in the system deployments include IBM, SGI and Cray, Inc. Read the Full Story.

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Hybrid Computing’s Radical Growth

 

Our GTC 2012 coverage continues as Dan Olds examines the growth of the CUDA environment from 150,000 downloads in 2007 to 1.5 million today:

More importantly, there are 35 NVIDIA-fueled hybrid supercomputers on the Top500 list today. The NDUT Tianhe-1A system, with 14,300 CPUs and 7,100 NVIDIA GPUs, held down the top spot on the list in 2010. The upcoming Oak Ridge Titan system will sport more than 18,000 CPUs alongside 18,000 GPUs, and should become the fastest supercomputer in the world sometime this fall.”

Read the Full Story.

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New Whitepaper: Dynamic Parallelism in CUDA

The details on Dynamic Parallelism were hard to find after the new feature was introduced as part of the GTC 2012 keynote yesterday. Now Nvidia has followed up with a short whitepaper that describes how it works.

Dynamic Parallelism in CUDA is supported via an extension to the CUDA programming model that enables a CUDA kernel to create and synchronize new nested work. Basically, a child CUDA Kernel can be called from within a parent CUDA kernel and then optionally synchronize on the completion of that child CUDA Kernel. The parent CUDA kernel can consume the output produced from the child CUDA Kernel, all without CPU involvement.

Download the whitepaper (PDF).

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Swimming in Sensors, Drowning in Data

Dan Olds from Gabriel Consulting Group shares his amazement from a GTC 2012 talk by MotionDSP.

Cleaning up and enhancing video is a tall order, compute-wise… But I just saw a demo of that in a GTC12 session run by MotionDSP. Their specialty is processing video streams from mobile platforms (think drones and airplanes) on the fly. We’re talking full motion, 30 frames per second video streams that are enhanced, cleaned up, and highly analyzable in real time. The amount of processing they’re doing is incredible. Lighting is enhanced, edges are enhanced, jitter is taken out, and the on-screen metadata (time, location, speed, etc.) is masked… The effect is profound. In the demo, what was once just a vague gray ship (which seemed to be vibrating like a can in a paint shaker) was clarified so that you could easily see what kind of ship it was and also see two suspicious figures milling around on deck. To me, it looked like there were enough pixels to enhance the video even further – to the point where we could identify the figures.”

Read the Full Story.

 

Also posted in Events, GPUs, GTC - GPU Technology Conference, HPC Hardware, Visualization | Leave a comment

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