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Inria Joins OpenMP ARB

“Inria teams have been developing runtime systems and compiler techniques for parallel programming over several decades.” says Olivier Aumage, researcher at Inria’s team STORM, “By joining the OpenMP ARB today, Inria looks forward to contribute this expertise in making OpenMP meet the challenges of the Exascale era”.

Superior Performance Commits Kyoto University to CPUs Over GPUs

In this special guest feature, Rob Farber writes that a study done by Kyoto University Graduate School of Medicine shows that code modernization can help Intel Xeon processors outperform GPUs on machine learning code. “The Kyoto results demonstrate that modern multicore processing technology now matches or exceeds GPU machine-learning performance, but equivalently optimized software is required to perform a fair benchmark comparison. For historical reasons, many software packages like Theano lacked optimized multicore code as all the open source effort had been put into optimizing the GPU code paths.”

Supercomputing Better Engines at Argonne

Researchers are using Argonne supercomputers to jump-start internal-combustion engine designs in the name of conservation. “Improving engine efficiencies by even a few percentage points can take a big chunk out of our carbon footprint. We are working on a proof-of-concept to demonstrate how simulating several thousand engine configurations simultaneously can really help engineers zero in on the optimum engine designs and operating strategies to maximize efficiency while minimizing harmful emissions.”

Podcast: Intel Scalable System Framework Moves HPC Forward at the System Level

In this Intel Chip Chat podcast, Alyson Klein and Charlie Wuischpard describe Intel’s investment to break down walls to HPC adoption and move innovation forward by thinking at a system level. “Charlie discusses the announcement of the Intel Xeon Phi processor, which is a foundational element of Intel Scalable System Framework (Intel SSF), as well as Intel Omni-Path Fabric. Charlie also explains that these enhancements will make supercomputing faster, more reliable, and increase efficient power consumption; Intel has achieved this by combining the capabilities of various technologies and optimizing ways for them to work together.”

Simulating Sea Ice Leads at DKRZ

Researchers at DKRZ are using supercomputers to better understand the movement of sea ice. “Sea ice is an important component of the Earth System, which is often being discussed in terms of integrated quantities such as Arctic sea ice extent and volume.”

Video: Mellanox Powers Open Science Grid on Comet Supercomputer

“We are pioneering the area of virtualized clusters, specifically with SR-IOV,” said Philip Papadopoulos, SDSC’s chief technical officer. “This will allow virtual sub-clusters to run applications over InfiniBand at near-native speeds – and that marks a huge step forward in HPC virtualization. In fact, a key part of this is virtualization for customized software stacks, which will lower the entry barrier for a wide range of researchers by letting them project an environment they already know onto Comet.”

Interview: PDSW-DISCS’16 Workshop to Focus on Data-Intensive Computing at SC16

The first Joint International Workshop on Parallel Data Storage and Data Intensive Scalable Computing Systems (PDSW-DISCS’16) has issued its Call for Papers. As a one day event held in conjunction with SC16, the workshop will combine two overlapping communities to to address some of the most critical challenges for scientific data storage, management, devices, and processing infrastructure. To learn more, we caught up with workshop co-chairs Dean Hildebrand (IBM) and Shane Canon (LBNL).

Preliminary Agenda Posted for HPC User Forum in Austin, Sept. 6-8

IDC has published the preliminary agenda for their next HPC User Forum. The event will take place Sept. 6-8 in Austin, Texas.

Podcast: Steve Scott on How Intel Xeon Phi is Fueling HPC Innovation at Cray

In this Intel Chip Chat podcast with Allyson Klein, Cray CTO Steve Scott describes the collaboration between Cray and Intel on the Intel Xeon Phi Processor for supercomputer integration. Steve highlights that Cray chose to implement the new Intel Xeon Phi Processor for its supercomputers because of the potential to support a diverse array of customer needs and deliver the best performance per application. He emphasizes that Cray software tools are key to optimizing Intel Xeon Phi processor performance at the system level.

University of Tokyo Selects Mellanox EDR InfiniBand

Today Mellanox announced that the University of Tokyo has selected the company’s Switch-IB 2 EDR 100Gb/s InfiniBand Switches and ConnectX-4 adapters to accelerate its new supercomputer for computational science.