“Phase one at CINECA, an academic consortium, was completed in May 2016 – coming in at 1.7 Petaflops, which at the time it was the largest Intel Omni-Path Fabric system in the world. Lenovo and CINECA are pleased to announce the delivery and installation of phase two, a 3,600 node Intel Xeon Phi processor which is interconnected with 100Gb Intel Omni-Path fabric – delivering 6.2 Petaflops of performance.”
“Researchers can run one cluster for 10,000 hours or 10,000 clusters for one hour anytime, from anywhere, and both cost the same in the cloud. And with the availability of Public Data Sets in Amazon S3, petabyte scale data is instantly accessible in the cloud. Attend and learn how to build HPC clusters on the fly, leverage Amazon’s Spot market pricing to minimize the cost of HPC jobs, and scale HPC jobs on a small budget, using all the same tools you use today, and a few new ones too.”
Today Fujitsu today announced the completion of the Oakforest-PACS supercomputer at the Joint Center for Advanced High Performance Computing (JCAHPC), which is jointly run by the University of Tokyo and the University of Tsukuba, and that operations have commenced today. This new supercomputer is comprised of FUJITSU Server PRIMERGY CX600 M1 x86 servers. It uses […]
“Software Defined Visualization (SDVis) is an open source initiative from Intel and industry collaborators to improve the visual fidelity, performance and efficiency of prominent visualization solutions – with a particular emphasis on supporting the rapidly growing “Big Data” usage on workstations through HPC supercomputing clusters without the memory limitations and cost of GPU based solutions. Existing applications can be enhanced using the high performing parallel software rendering libraries OpenSWR, Embree, and OSPRay. At the Intel HPC Developer Conference, Amstutz provided an introduction to this initiative, its benefits, a brief descriptions of accomplishments in the past year and talk about the changes made to Intel provided libraries in the past year.”
ANSYS, HLRS and Cray have pushed the boundaries of supercomputing by achieving a new supercomputing milestone by scaling ANSYS software to 172,032 cores on the Cray XC40 supercomputer, hosted at HLRS, running at 82 percent efficiency. This is nearly a 5x increase over the record set two years ago when Fluent was scaled to 36,000 cores. “This record-setting scaling of ANSYS software on the Cray XC40 supercomputer at HLRS proves that close collaborations with customers and partners can produce exceptional results for running complex simulations,” said Fred Kohout, senior vice president and chief marketing officer at Cray.
How is Hewlett Packard Enterprise reinventing the fundamental architecture on which all computers have been built for the past 60 years? In this video, HPC describes the evolution of The Machine research project – one of the largest and most complex research projects in the company’s history – and how HPE demonstrated the world’s first Memory-Driven Computing architecture.
The Euro-Par 2017 conference has issued its Call for Papers. The conference takes place Aug. 28 – Sept. 1, 2017 in Santiago de Compostela, Spain. Euro-Par is the prime European conference covering all aspects of parallel and distributed processing, ranging from theory to practice, from small to the largest parallel and distributed systems and infrastructures, from […]
In this video from SC16, Ben Sander from AMD presents: HIP and CAFFE Porting and Profiling with AMD’s ROCm. “We are excited to present ROCm, the first open-source HPC/Hyperscale-class platform for GPU computing that’s also programming-language independent. We are bringing the UNIX philosophy of choice, minimalism and modular software development to GPU computing. The new ROCm foundation lets you choose or even develop tools and a language run time for your application. ROCm is built for scale; it supports multi-GPU computing in and out of server-node communication through RDMA.”
“When designing an application that contains many threads and less cores than threads, it is important to understand what is the optimal number of threads that should be assigned to a core. This value should be parameterized, in order to easily run tests to determine which is the optimum value for a given machine. One thread per core on the Intel Xeon Phi processor will give the highest performance per thread. When the number of threads per core is set at two or four, the individual thread performance may be lower, but the aggregate performance will be greater.”
In this video from SC16, Silicon Mechanics CTO Daniel Chow describes how the company brings value and performance to its HPC customers. “When looking for a leading solutions integrator to couple disparate hardware and software products into a “HPC Built For You” solution, that will keep up with the evolution and disruptive forces in technology – the Experts at Silicon Mechanics are here to help you.”