Dan Stanzione from TACC presented this keynote at the recent MVAPICH User Group. “The Stampede system began production operations in January 2013. The system was one of the largest ever deployments of MVAPICH, with a 6,400 node FDR Infiniband fabric connecting more than 2PF of Intel Xeon processors. The system also was the first large scale installation of the Intel many core Xeon Phi Co-Processors, which also used MVAPICH for communications. This talk will discuss the experiences over the first 1.5 years of production with MVAPICH and Stampede.”
In this podcast, the Radio Free HPC team looks at the Zennet initiative, a “public, distributed, and decentralized Supercomputer.” As the brainchild of Israeli computer scientist Ohad Asor, Zennet is essentially a free-market alternative to AWS that sounds a lot like the marriage of BitCoin and SETI@Home.
Today IBM announced a collaboration with Deutsches Elektronen-Synchrotron (DESY) in Germany to speed access to 20 GB of data/second flowing from its PETRA III accelerator, which is used by 2000 global scientists to explore the building blocks of matter. Based on the IBM Elastic Storage that powered Watson in its historic win on Jeopardy!, this Big Data architecture will speed up analysis of massive volumes of x-ray images of atom-sized particles, and can aid variety of research projects ranging from semiconductor designs to cancer therapies.
In a quest to design synthetic microorganisms for alternate fuel sources, Howard Salis from Penn State leveraged AWS to bring supercomputing resources to scientists. “The DNA Compiler has fundamentally changed the way that genetic engineering takes place by providing a way to quantitatively control and optimize the expression of many proteins working together, instead of performing trial-and-error DNA mutagenesis.”
In this video, Barry Davis from Intel describes the company’s new Omni Scale Fabric, an integrated, high performance interconnect designed for CPU to CPU communications. “”Intel is re-architecting the fundamental building block of HPC systems by integrating the Intel Omni Scale Fabric into Knights Landing, marking a significant inflection and milestone for the HPC industry,” said Charles Wuischpard, vice president and general manager of Workstations and HPC at Intel. “Knights Landing will be the first true many-core processor to address today’s memory and I/O performance challenges. It will allow programmers to leverage existing code and standard programming models to achieve significant performance gains on a wide set of applications. Its platform design, programming model and balanced performance makes it the first viable step towards exascale.”
In this slidecast, Mike Black from Micron describes the company’s Hybrid Memory Cube technology for the next-generation Xeon Phi processor, codenamed Knights Landing. “Delivering 5X the sustained memory bandwidth versus DDR4 with one-third the energy per bit in half the footprint, the Knights Landing high performance, on package memory combines high-speed logic and DRAM layers into one optimized package that will set a new industry benchmark for performance and energy efficiency.”