SC16 has extended the application deadline for its Impact Showcase, a forum designed to show attendees why HPC Matters in the real world. Submissions are now due Sept. 15.
Over at the SC16 Blog, JP Vetters writes that planning for the SCinet high-bandwidth conference network is a multiyear process. “The success of any large conference depends on the, often unseen, hard work of many. During the last quarter century, the SCinet team has strived to perfect its routine so that conference-goers can experience a smoothly run Show.”
George Slota presented this talk at the Blue Waters Symposium. “In recent years, many graph processing frameworks have been introduced with the goal to simplify analysis of real-world graphs on commodity hardware. However, these popular frameworks lack scalability to modern massive-scale datasets. This work introduces a methodology for graph processing on distributed HPC systems that is simple to implement, generalizable to broad classes of graph algorithms, and scales to systems with hundreds of thousands of cores and graphs of billions of vertices and trillions of edges.”
Today ACM announced the recipients of the 2016 ACM/IEEE George Michael Memorial HPC Fellowships. The fellowship honors exceptional PhD students throughout the world whose research focus is on high performance computing applications, networking, storage or large-scale data analytics using the most powerful computers that are currently available.
In this video from the 4th Annual MVAPICH User Group, DK Panda from Ohio State University presents: Overview of the MVAPICH Project and Future Roadmap. “This talk will provide an overview of the MVAPICH project (past, present and future). Future roadmap and features for upcoming releases of the MVAPICH2 software family (including MVAPICH2-X, MVAPICH2-GDR, MVAPICH2-Virt, MVAPICH2-EA and MVAPICH2-MIC) will be presented. Current status and future plans for OSU INAM, OEMT and OMB will also be presented.”
IDC has announced the featured speakers for the next international HPC User Forum. The event will take place Sept. 22 in Beijing, China.
The Fujitsu Journal has posted details on a recent Hot Chips presentation by Toshio Yoshida about the instruction set architecture (ISA) of the Post-K processor. “The Post-K processor employs the ARM ISA, developed by ARM Ltd., with enhancements for supercomputer use. Meanwhile, Fujitsu has been developing the microarchitecture of the processor. In Fujitsu’s presentation, we also explained that our development of mainframe processors and UNIX server SPARC processors will continue into the future. The reason that Fujitsu is able to continuously develop multiple processors is our shared microarchitecture approach to processor development.”
Over at the ARM Community Blog, Nigel Stephens writes that the company has introduced scalable vector extensions (SVE) their A64 instruction set to bolster high performance computing. Fujitsu is developing a new HPC processor conforming to ARMv8-A with SVE for the Post-K computer.
In this video from the 2016 Blue Waters Symposium, GPU Performance Nuggets – Carl Pearson and Simon Garcia De Gonzalo from the University of Illinois present: GPU Performance Nuggets. “In this talk, we introduce a pair of Nvidia performance tools available on Blue Waters. We discuss what the GPU memory hierarchy provides for your application. We then present a case study that explores if memory hierarchy optimization can go too far.”
For the first time, SC16 will offer childcare in the convention center to registered attendees and exhibitors. “This will provide an opportunity for the family to be together while one or both parents enjoy either parts or all of the conference. Of course, it is entirely optional, but we listened to our audience and this seemed to be a growing need. I realize this is a small step, but hopefully it is the first of many more small steps to come.”