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New ORNL Paper: Survey on Asymmetric Multicore Processors


ORNL researcher Sparsh Mittal has authored a new paper entitled “A Survey Of Techniques for Architecting and Managing Asymmetric Multicore Processors.” Now accepted for ACM Computing Surveys 2015, the document reviews nearly 125 papers.

It’s Here: The Print ‘n Fly Guide to SC15 in Austin


At insideHPC, are very pleased to publish the Print ‘n Fly Guide to SC15 in Austin. We designed this Guide to be an in-flight magazine custom tailored for your journey to SC15 — the world’s largest gathering of high performance computing professionals.

Council on Competitiveness Report: HPC Transforms Manufacturing


Today the Council on Competitiveness published a new report from the National Digital Engineering Manufacturing Consortium (NDEMC). Entitled “Modeling, Simulation and Analysis, and High Performance Computing: Force Multiplier for American Innovation,” the 88 age report explores how HPC transforms manufacturing.

New Paper: Can 3D-Stacking Topple the Memory Wall?

Memory latency depends on the used memory bandwidth, and the memory latency-bandwidth curve has three regions — constant, linear and exponential. Moving from conventional DDRx (upper figure) to high-bandwidth memory solutions (lower figure) will significantly reduce memory latency only for workloads located in theexponential region of the DDRx latency-bandwidth curve.

Can 3D-stacking technology topple the long-standing “memory wall” that’s been holding back HPC application performance? A new paper from the Barcelona Supercomputing Center written in collaboration with experts from Chalmers University and Lawrence Livermore National Laboratory concludes that it will take more than just the simple replacement of conventional DIMMs with 3D-stacked devices.

Video: Worldwide HPC Market & 2015-2019 Market Forecast

Michael Feldman, Intersect360 Research

“Intersect360 Research’s annual HPC market model and forecast shows modest growth in 2014. Despite ongoing weakness in the public sector, commercial usage of HPC drove the market to $29.4 billion in 2014, a year-over-year growth of 2.8%. As applications for high-performance technologies expand, the market is projected to grow at a compound annual rate of 4.2% through 2019.”

UberCloud Publishes 3rd Compendium of HPC Cloud Case Studies


The UberCloud has published their 3rd Compendium of HPC Cloud Case Studies. Like its predecessors in 2013 and 2014, this year’s edition draws from a select group of projects undertaken as part of the UberCloud Experiment. “Our efforts are paying off. Based on the experience gained over the past several years, we have now increased the success rate of the individual experiments to almost 100%, as compared to 40% in 2013 and 60% in 2014.”

DDN Sets World Record STAC Performance


Today DDN announced record performance on the Securities Technology Analysis Center (STAC) benchmark. Using the company’s EXAScaler storage solution, DDN set new public records for multiple workload types and sizes, including large and small workloads as well as I/O and compute-intensive workloads.

New Whitepaper: Multi-Threading and Parallel Reduction for Xeon Phi


Colfax Research has published a new whitepaper entitled: Multi-Threading and Parallel Reduction. As part 1 of a 3-part educational series, the paper authored by Ryo Asai and Andrey Vladimirov focuses on optimization of applications for the Intel Xeon processors and Intel Xeon Phi coprocessors.

New Report Surveys CPU-GPU Heterogeneous Computing Techniques


A new paper from ORNL’s Sparsh Mittal and Jeffrey Vetter seeks to change the mindset of researchers using GPUs. Entitled, “A Survey of CPU-GPU Heterogeneous Computing Techniques,” the paper contends that merely offloading computational tasks to GPUs is not optimal, instead, using both CPU and GPU can lead to potentially higher speedup.

Smart Manufacturing with a Digital Thread


The National Institute of Standards and Technology (NIST) is leading a collaborative project with industrial partners to standardize 3-D models to exchange information across design and manufacturing in one seamless “digital thread.” The Design to Manufacturing and Inspection Project will make use of a new international standard for incorporating computer-readable product and manufacturing information (PMI) into 3D models that do not require human interpretation of graphical depictions and data re-entry.