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Nested Parallelism

phi-compressor

The benefits of nested parallelism on highly threaded applications can be determined and quantified. With the number of cores in both the host CPU (Intel Xeon) and the coprocessor (Intel Xeon Phi) continues to increase, much thought must be given to minimizing the thread overhead when many threads need to be synchronized, as well as the memory access for each processor (core). Tasks that can be spread across an entire system to exploit the algorithm’s parallelism, should be mapped to the NUMA node to make them more efficient.

Lustre* For the Enterprise

lustre

Lustre* is not just for the national labs any longer. It was born out of serving up data extremely fast to the world’s most powerful HPC clusters using parallel I/O to improve performance and scalability. Here are five reasons why Lustre is enterprise-ready.

Quantum Chemistry at Scale

quantum chemistry

“Applications can be tuned to use both the Intel Xeon and the Intel Xeon Phi simultaneously, without modifying the code to just run on the coprocessor. Using a number of software tools from Intel, performance of a coupled cluster method can be demonstrated to gain a tremendous performance with excellent scaling.”

High Performance Computing in Defense Intelligence

onestop_truck

Technological advancements in hardware and software products allow analysts to process larger amounts of data rapidly, allowing them time to apply human judgment and experience to intelligence problems. This article examines a couple of the hardware advancements in HPC.

Coprocessor File System Support

phi-compressor

To get maximum performance from the Intel Xeon Phi, applications may have to be re-thought to take advantage of the SIMD architecture.

Invest in Supercomputers, Not Chillers

Mississippi State

By using Direct-to-Chip liquid cooling, Mississippi State University was able to purchase more servers by minimizing the capital spent to cool the data center. The success of the initial cluster at MSU led to the installation of second cluster.

Why Modernize Code?

Intel_HPC_CodeM_IDZweb_HERO_375x420

In order to speed up applications, a developer must learn to take advantage of the multiple threads, cores and sockets found on a single server or on a cluster. Just hoping for a faster CPU anymore won’t cut it.

South Africa’s CHPC Builds a Better Infrastructure with Altair PBS Works

CHPC South Africa

At the Centre for High-Performance Computing (CHPC) in South Africa, the mission is to enable cutting-edge research by supporting the highest levels of HPC available. That means ensuring researchers – who often are not experienced with computers let alone HPC systems – to get their work done with the HPC getting in the way.

Integrating an Intel Xeon Phi Cluster

Cray_Computer_Cluster_05_HRSS

At the National Institute of Computational Sciences (NICS), a joint venture by the University of Tennessee and the Oak Ridge National Laboratory, a joint team set out to learn how to integrate the Intel Xeon Phi coprocessor into cluster configurations.

Power Usage for Coprocessors

PS5666X

“As the use of coprocessors increases to speedup HPC applications, it is important to understand how much additional power the coprocessors use. With various measurements and benchmarks arising to calculate the power used during the running of compute and data intensive applications, measuring the power draw from an Intel Xeon Phi coprocessor is important to understanding the best use of resources.”