MailChimp Developer

Sign up for our newsletter and get the latest HPC news and analysis.
Send me information from insideHPC:


Registration Opens for Inaugural Nimbix Developer Summit in Dallas

Registration is now open for the inaugural Nimbix Developer Summit. With an impressive lineup of speakers & sponsors from Mellanox, migenius, Xilinx, and more, the event takes place March 15 in Dallas, Texas. “The summit agenda will feature topics such as hardware acceleration, coprocessing, photorealistic rendering, bioinformatics, and high performance analytics. The sessions will conclude with a panel of developers discussing how to overcome challenges of creating and optimizing cloud-based applications.”

European ExaNeSt Project to Pave the Way to Exascale

Today the European Consortium announced a step towards Exascale computing with the ExaNeSt project. Funded by the Horizon 2020 initiative, ExaNeSt plans to build its first straw man prototype in 2016. The Consortium consists of twelve partners, each of which has expertise in a core technology needed for innovation to reach Exascale. ExaNeSt takes the sensible, integrated approach of co-designing the hardware and software, enabling the prototype to run real-life evaluations, facilitating its scalability and maturity into this decade and beyond.

Do IT Systems Joins Bright Partner Program

Today Bright Computing announced that Italy-based Do IT Systems has signed up to the Bright Partner Program. “Together, Bright Computing and Do IT Systems offer a compelling proposition for Italian customers that require high quality HPC solutions and remote HPC management,” said Roberto Strano, Technical Manager at Do IT Systems. “We have been very impressed with the Bright software, and we are confident that it will enable our customers to develop and manage HPC clusters in an affordable and efficient way.”

Allinea Scalable Profiler Speeds Application Readiness for Summit Supercomputer at Oak Ridge

Today Allinea announced that Oak Ridge National Laboratory has deployed its code performance profiler Allinea MAP in strength on the Titan supercomputer. Allinea MAP enables developers of software for supercomputers of all sizes to produce faster code. Its deployment on Titan will help to use the system’s 299,008 CPU cores and 18,688 GPUs more efficiently. Software teams at Oak Ridge are also preparing for the arrival of the next generation supercomputer, the Summit pre-Exascale system – which will be capable of over 150 PetaFLOPS in 2018.

Video: Vectorization Advisor in Action for Computer-Aided Formulation

In this video from the Intel HPC Developer Conference at SC15, Kevin O’Leary from Intel presents: Vectorization Advisor in Action for Computer-Aided Formulation. “The talk will focus on a step-by-step walkthrough of optimizations for an industry code by using the new Vectorization Advisor (as part of Intel® Advisor XE 2016). Using this tool, HPC experts at UK Daresbury Lab were able to spot new SIMD modernization and optimization opportunities in the DL_MESO application – an industry engine currently used by “computer-aided formulation” companies like Unilever.”

Job of the Week: HPC Compiler & Tools Engineer at LLNL

Lawrence Livermore National Lab is seeking an HPC Compiler & Tools Engineer in our Job of the Week. “As a member of the Development Environment Group in the Livermore Computing (LC) supercomputing center, will work as a software developer specializing in compilers and application development tools for supporting High Performance Computing (HPC). Will work with scientific computing teams, the open source software community, and HPC vendor partners on the development of enabling technologies for the state-of-the-art platforms currently in use and under procurement.”

Allinea Tools Help Deliver 30% Performance Boost in Reservoir Simulation

Today Allinea reports that developers of Roxar Software Solutions at Emerson Process Management used the Allinea Forge to increase the performance of their Tempest MORE next-generation reservoir simulator by 30 percent.

InfiniBand Enables Intelligent Networks

“The path to Exascale computing is clearly paved with Co-Design architecture. By using a Co-Design approach, the network infrastructure becomes more intelligent, which reduces the overhead on the CPU and streamlines the process of passing data throughout the network. A smart network is the only way that HPC data centers can deal with the massive demands to scale, to deliver constant performance improvements, and to handle exponential data growth.”

HiPEAC16 Conference Returns to Prague January 18-20

The HiPEAC16 High Performance and Embedded Architecture and Compilation conference returns to Prague next week. With three keynote talks, 33 workshops, nine tutorials, and 37 papers, the three-day conference takes place January 18-20.

Video: Intel Black Belt Discussion on HPC Code Modernization

In this video from the Intel HPC Developer Conference at SC15, James Reinders hosts an Intel Black Belt discussion on Code Modernization. “Modern high performance computers are built with a combination of resources including: multi-core processors, many core processors, large caches, high speed memory, high bandwidth inter-processor communications fabric, and high speed I/O capabilities. High performance software needs to be designed to take full advantage of these wealth of resources. Whether re-architecting and/or tuning existing applications for maximum performance or architecting new applications for existing or future machines, it is critical to be aware of the interplay between programming models and the efficient use of these resources. Consider this a starting point for information regarding Code Modernization. When it comes to performance, your code matters!”