“The path to Exascale computing is clearly paved with Co-Design architecture. By using a Co-Design approach, the network infrastructure becomes more intelligent, which reduces the overhead on the CPU and streamlines the process of passing data throughout the network. A smart network is the only way that HPC data centers can deal with the massive demands to scale, to deliver constant performance improvements, and to handle exponential data growth.”
The HiPEAC16 High Performance and Embedded Architecture and Compilation conference returns to Prague next week. With three keynote talks, 33 workshops, nine tutorials, and 37 papers, the three-day conference takes place January 18-20.
In this video from the Intel HPC Developer Conference at SC15, James Reinders hosts an Intel Black Belt discussion on Code Modernization. “Modern high performance computers are built with a combination of resources including: multi-core processors, many core processors, large caches, high speed memory, high bandwidth inter-processor communications fabric, and high speed I/O capabilities. High performance software needs to be designed to take full advantage of these wealth of resources. Whether re-architecting and/or tuning existing applications for maximum performance or architecting new applications for existing or future machines, it is critical to be aware of the interplay between programming models and the efficient use of these resources. Consider this a starting point for information regarding Code Modernization. When it comes to performance, your code matters!”
OpenHPC is a collaborative, community effort that initiated from a desire to aggregate a number of common ingredients required to deploy and manage High Performance Computing Linux clusters including provisioning tools, resource management, I/O clients, development tools, and a variety of scientific libraries.
“Developers of modern HPC applications face a challenge when scaling out their hybrid (MPI/OpenMP) applications. As cluster sizes continue to grow, the amount of analysis data collected can easily become overwhelming when going from 10s to 1000s of ranks and it’s tough to identify which are the key metrics to track. There is a need for a lightweight tool that aggregates the performance data in a simple and intuitive way, provides advice on next optimizations steps, and hones in on performance issues. We’ll discuss a brand new tool that helps quickly gather and analyze statistics up to 100,000 ranks. We’ll give examples of the type of pertinent information collected at high core counts, including memory and counter usage, MPI and OpenMP imbalance analysis, and total communication vs. computation time. We’ll work through analyzing an application and effective ways to manage the data.”
“In this presentation, we will discuss several important goals and requirements of portable standards in the context of OpenMP. We will also encourage audience participation as we discuss and formulate the current state-of-the-art in this area and our hopes and goals for the future. We will start by describing the current and next generation architectures at NERSC and OLCF and explain how the differences require different general programming paradigms to facilitate high-performance implementations.”
The High Performance Conjugate Gradients (HPCG) benchmark continues to gain traction in the high-performance computing community. “HPCG is designed to complement the traditional High Performance Linpack (HPL) benchmark used as the official metric for ranking the top 500 systems,” said Sandia National Laboratories researcher Mike Heroux, who developed the HPCG program in collaboration with Jack Dongarra and Piotr Luszczek from the University of Tennessee.
Scientists from the Heat and Mass Transfer Technological Center (CTTC) at the Technical University of Catalonia in Spain have harnessed the extreme performance of the Mira supercomputer with their in-house multi-physics CFD code as a result of collaboration on scalable debugging for the high-end system between Allinea Software and Argonne National Laboratory.
“The goal of each hackathon is for current or prospective user groups of large hybrid CPU-GPU systems to send teams of at least 3 developers along with either (1) a (potentially) scalable application that needs to be ported to GPU accelerators, or (2) an application running on accelerators which needs optimization. There will be intensive mentoring during this 5-day hands-on workshop, with the goal that the teams leave with applications running on GPUs, or at least with a clear roadmap of how to get there. Our mentors come from national laboratories, universities and vendors, and besides having extensive experience in programming with OpenACC/CUDA, many of them develop the GPU-capable compilers and help define the OpenACC standard.”
Today Allinea released version 6.0 of their HPC development tools suite Allinea Forge and Performance Reports. Building on their commitment to serving the scientific HPC community, Allinea demonstrated the new features at SC15 last month in Austin.