By Timothy Prickett Morgan • Get more from this author

Boffins at IBM have come up with a better way to embed laser communications onto processor and memory chips using plain vanilla CMOS manufacturing processes, paving the way for three-dimensional chips integrating hundreds of processors, their main memory, and on-chip optical networks that will, it is hoped, allow for the creation of power-efficient exascale systems. And really fast workstations for playing Crysis, of course.

IBM’s techies have been working for more than a decade to try to figure out how to integrate optical signaling inside of chips and between collections of chips because optics can pack more bandwidth into a given space than an etched wire on a chip. Moreover, it takes a lot more energy to push an electric signal off a chip than it does to send a laser pulse.

The problem has been that embedding communication lasers onto chips – what is called silicon photonics – required non-standard and expensive chip manufacturing techniques rather than the standard CMOS lithography used to make processors and other chips used in systems today.

The breakthrough that Big Blue is talking about at the SemiCon conference in Tokyo today is being able to embed silicon nanophotonics components such as modulators, germanium photodetectors, and ultra-compact wavelength division multiplexers onto normal analog and digital CMOS chips with just a few added steps in the wafer baking process.

The wave division multiplexers allow laser light of different colors to share the same optical channel, thereby allowing for multiple signals to be sent in parallel and thereby significantly boosting signals over what can be accomplished over a single wavelength using optics or over chip channels or copper wires using electrical signals.

“Our CMOS integrated nanophotonics breakthrough promises unprecedented increases in silicon chip function and performance via ubiquitous low-power optical communications between racks, modules, chips, or even within a single chip itself,” explained Yurii Vlasov, manager of the silicon nanophotonics department at IBM Research, in a statement announcing the breakthrough. “The next step in this advancement is to establishing manufacturability of this process in a commercial foundry using IBM deeply scaled CMOS processes.”

In its SemiCon presentation, which you can see here, IBM showed off a project called Sniper, which it started in 2008 and which is short for silicon nanoscale integrated photonic and electronic transceiver. (Yes, we realize that this acronym is really SNIPET, but IBM’s boffins apparently didn’t think this sounded cool, so they broke the rules of abbreviation as tech companies so often do.)

IBM is showing off the performance specs of the ring oscillator, receiver amplifier, transmitter modulator driver, waveguides, edge fiber coupler, wavelength division multiplexer (WDM), germanium detector, modulators, and switches in the nanophotonics components, which are all assembled together here:

IBM's Sniper silicon nanophotonics chip project

IBM’s Sniper silicon nanophotonics chip project
This Sniper test chip uses 130 nanometer processes for the CMOS portions of the chip and 65 nanometer processes for the nanophotonics. The design puts a six-channel WDM onto the chip in 1.26 square millimeters and six receiver channels in 1.86 square millimeters.

With all the auxiliary circuits, IBM says it can put a nanophotonics transceiver channel onto a CMOS chip in a half square millimeter, which is an order of magnitude better than the 6 square millimeters per transceiver channel it takes for other on-chip optics techniques to do today. These other techniques do the germanium optics components last and require big changes to the wafer baking process, too, which is disruptive. IBM has over 30 patents on the processes it has created to embed the photonics onto chips.

IBM’s long-term plan is to be able to plunk down transceivers that can handle 1 Tb/sec of bandwidth in a 16 square millimeter portion of a chip. And further down the road, the concept is to build 3D chips that layer processors, their main memory, and a nanophotonic network linking these chips together into a single package and to the outside world, thus:

Conceptual rendering of a stacked chip with nanophotonic interconnects

Conceptual rendering of a stacked chip with nanophotonic interconnects
The Tb/sec of bandwidth in the on-chip optical transceivers is a requirement for linking processor cores together to push up into the exascale performance range. (Exaflops if you are talking about math, but integer operations also count for lots of work.)

The processor cores will hook into a CMOS serializer with parallel channels delivering that aggregate 1 Tb/sec of bandwidth into and out of the chip; this will in turn feed into the CMOS driver, which links to the optical modulator and then onwards into the wavelength division multiplexer. The WDMs are hooked together by optical switching circuits, and the process is reversed to get back through the optical and electronic components to another processor core in the chip complex.

Here’s the funny bit. IBM says that to reach the exascale performance level, a system will have to have on the order of 100 million optical channels – as much as exist today in all of the parallel optical links in the world. The “Blue Waters” massively parallel Power7-based supercomputer, which has its own proprietary optical network lashing its nodes together, has a million optical links to reach its 10 petaflops of peak performance. (The Blue Waters machine will be installed at the University of Illinois next year, and El Reg gave you the feeds and speeds on the system here.)

If you are wondering why IBM is not exactly jumping on the GPU co-processor bandwagon as it contemplates exascale computing, now you know why. IBM seems to be betting that it can shrink down a Blue Waters or BlueGene supercomputer using optical interconnects and sandwiching memory between processors and an on-chip optical network. The processors and the optical network may turn out to be the easy part – memory technology is not keeping up. ®

This article was originally published at The Register.