Analysis If you want to get into the server processor racket, here’s some advice: Don’t bring a knife to a gun fight. And when you whip out your guns, you better have a piece stashed in each of your boots, maybe another high-caliber rifle on your back, and a few knives while you are at it for price-cutting when the bullets run out.

With Intel getting ready to launch its “Sandy Bridge” Xeon E5 processors in March and revving up its 22 nanometer processes to eventually field “Ivy bridge” kickers, Advanced Micro Devices is going to have to engineer some pretty impressive new Opteron server chips. It’ll have to cook up those chips pretty sharpish, in conjunction with its wafer-baking partners, if it hopes to gain ground in the ongoing x86 server chip war – much less hold the hard-fought ground it has attained in high performance computing and server virtualization.

Back in the early 2000s, Intel was trying to protect its high-end 64-bit Itanium server business and push its Xeon processors down into the 32-bit volume server space, and AMD brilliantly shot the gap between the Xeon and Itanium to create the 64-bit Opterons, eventually pushing its server market share as high as 25 per cent.

But it has been a long time since x86 server chip juggernaut Intel was hammered – SledgeHammered, to be specific – by longtime rival AMD with its 64-bit, low-power, multicore Opteron processors. Intel shifted to the Core microarchitecture, added 64-bit memory addressing and processing, and a slew of key features such as the QuickPath Interconnect to its Xeon processors and hit back hard against the Opteron upstart. The “Nehalem” Xeon architecture announced in 2009 had everything that Opterons had, and when the Great Recession hit just in the wake of yet another Opteron delay, server makers put most of their effort into build Xeon war machines, not Opteron battlewagons, and AMD has been losing ground ever since.

Because server chip profits help pay the bills at Intel, AMD, IBM, Oracle, and Fujitsu, the loss of market share by AMD is one of the key reasons why CEO Dirk Meyer resigned in January 2011. In hindsight, we can also see that Meyer and the bulk of the management team that handles chip development and manufacturing have been replaced since new CEO Rory Read came aboard last July. AMD has a new CTO – Mark Papermaster, formerly of IBM, Apple, and Cisco Systems – and has replaced its former marketing, products, and operations bosses, and has tapped ex-Intel engineer Rajan Naik as senior vice president and chief strategy officer.

So, AMD is no doubt drawing up new war plans for the x86 server battlefield, but the company has not said much to date about its plans. Perhaps it will enlighten us during its Analyst Day this week. But we can conjecture about what AMD might do by looking at what Intel is about to do in the x86 racket.

A Sandy Bridge not too far

While Intel never publicly promised that the “Sandy Bridge-EP” Xeon E5 processors would launch last fall for shipments in the fourth quarter, the circumstantial evidence – and comments from motherboard and server makers like Super Micro – indicate that this was indeed the plan. But with AMD having its own issues shipping its “Interlagos” Opteron 6200 processors for two-socket and four-socket servers and its “Valencia” Opteron 4200s for single-socket and dual-socket machines, Intel did not have to rush to market. (The speculation is that a SAS controller bug similar to the one in the C200 chipset that delayed the launch of “Sandy Bridge-DT” E3 processors and various PC chips of similar design has been found in the “Patsburg” C600 chipset for the Xeon E5s. Intel has not confirmed this.) Frankly, with Intel turning in the best fourth quarter and fiscal year in its history, in terms of profits and revenues, as 2011 came to a close, despite a PC slowdown and whatever issues stalled the Xeon E5s, it is hard to argue that Intel made the wrong call.

Chip happens

Intel is just starting to talk to press and analysts under embargo this week about the forthcoming Xeon E5s, and it is no coincidence that it is doing so just ahead of AMD’s Analyst Day. (El Reg is reporting this to you from coach on a Delta flight to Portland, Oregon, ahead of a briefing by Intel from its Beaverton chip and server development labs.)

As El Reg exclusively disclosed last May, the plan with the Xeon E5s is to take what would have normally been a chip for general-purpose two-socket workhorses and bifurcate the line into multiple processor and chipset variants to address very precise market segments. This is, of course, what AMD did two years when it created two different two-socket server families: the Opteron 4100s – which could also scale down to single socket machines aimed at small, power-sensitive workloads – and the Opteron 6100s, which could scale up to four processor sockets.

Anything AMD can do, Intel can do. (The market decides if Intel can do it better, or at least well enough to allow IT managers to fall back on the “nobody ever got fired for buying Intel” insurance policy.)

Intel is actually cutting its server market into eight pieces with the Xeon E5 launch. That’s Itanium 9300s and Xeon 7500s and E7s at the high-end (and eventually the “Sandy Bridge-EX” E8s). That’s two segments of the market that share chipsets and memory cards, but that have different motherboards and sockets. At least until Intel finally delivers, as it is rumored to be in the works, the long-promised common Xeon-Itanium socket. That could happen with the E8s, but it is far more likely to happen with the “Ivy Bridge-EX” Xeon E9s years hence. At the low-end, there’s the single-socket Xeon E3 and Atom processors, depending on how wimpy or brawny your workload is. That’s four addressable server segments in total.

The Xeon E5s will also span four different server types and will cover the middle and overlap with the high and low ends. The Xeon E5-2600, as the first of the “Romley” server platforms are expected to be called, will use the “EP” variant of the Xeon E5 chip that plugs into the new “Socket R” CPU socket. This socket is not compatible with the current Xeon 5500 and 5600 processors, but has all sorts of goodies, including two QPI links between the processors, support for unregistered, registered, and load-reduced (LR) DDR3 main memory, and integrated PCI-Express 3.0 controllers on the processor. This is the chip that Intel has presumably been shipping under NDA to selected supercomputer and hyperscale data center customers since last fall. This chip is clearly aimed at two-socket Opteron 6200 machines.

For two-socket machines that don’t need all of these capabilities, Intel is expected to roll out its “Sandy Bridge-EN” chips, rumored to be called the Xeon E5-2400s. These chips will plug into the new “Socket B2″ socket and will sport only one QPI link between processors as well as fewer memory channels, fewer DIMMs per core, and fewer PCI-Express 3.0 slots. This chip is fired directly at two-socket Opteron 4200 iron.

If the rumors are right, then Intel will also ship a variant of the Sandy Bridge-EP chip that will be able to span four processor sockets in a single system image. This chip is expected to be called the Xeon E5-4600 and is obviously targeting the four-socket Opteron 6200.

And finally, Intel will field a Xeon E5-1600 chip, aimed at single-socket servers and workstations and based on the Sandy Bridge-EN chip that will zero in on single-socket Opteron 4200 servers and whatever plans AMD has to revive its single-socket server biz with the Opteron 3000 series, which it said it was working on back in November. The first Opteron 3000 chip, code-named “Zurich” and presumably to be named the Opteron 3200 to be consistent with the 2012 series of Opteron processors, is basically a cut-down Opteron 4200 with six or eight cores that will plug into an AM3+ socket instead of a C32 socket.

In any event, Intel appears to be looking to chase the microserver segment with the Xeon E5-1600 as AMD is looking to pursue with the Opteron 4200 and 3200 chips. The word on the street is that the Xeon E5-1600 will plug into the Socket R socket, but it would make more sense for it to use the lower-cost Socket B2 socket.

Should all of this come to pass in 2012, it is safe to say that Intel has a weapon to match everything that AMD can throw at it – and then some. AMD only has one flavor of four socket machine, and Intel has three if you count Itanium. AMD has only two kinds of single-socket boxes it can bring into the field, Intel has three if you count Atom. AMD has two two-socket boxes, but Intel has four if you count Itanium.

It’s Hammer time, again

It must have been such fun to run AMD when Intel’s server and PC chips were misaligned with the market needs. It must be daunting to come into work every day at AMD and see the lead in process technology, cash, clout, and chip and market coverage that Intel currently has not just over AMD, but over anyone who is making processors for anything larger than a smartphone or tablet.

AMD has also been winning the core count skirmish against Intel and positioning its two-core “Bulldozer” module used in the Opteron 4200s and 6200s as two strong physical threads against Intel’s weaker HyperThreaded cores. However, with a shared scheduler, on workloads that make heavy use of 256-bit floating point instructions, half of the 16 cores in an Opteron 6200 will often sit idle and the net effect is that the performance should be about the same as the forthcoming Xeon E5 with eight cores running 256-bit floating point. AMD has two stronger cores, but only if you want to do 128-bit math or integer work.

So what is AMD to do?

Go back to the drawing board and exploit whatever weaknesses it can find in Intel’s armor, just as always. Or, start a fight on a new battlefield where Intel is not going to be so strong.

Back in November 2010, two months before the management shakeup at AMD, the company said that its plan for this year was to bring out replacements for the C32 socket used for Opteron 4100 and 4200 processors and the G34 socket used with Opteron 6100 and 6200 processors.

The plan calls for the high-end Opterons, code-named “Terramar” and presumably called the Opteron 6300, to have 20 Bulldozer cores based on a next-generation core, code-named “Piledriver”. The low-end will get the “Sepang” Opteron 4300, a ten-core chip that is essentially what gets double-stuffed into a socket to make the Terramar chip package. Rumor has it that AMD will boost memory capacity with these forthcoming Opterons as well as support PCI-Express 3.0 peripherals. The Terrarmar and Sepang chips will be etched in the 32 nanometer processes used by GlobalFoundries, AMD’s spun out former chip manufacturing operations.

Presumably there is a process shrink to 28 nanometers to boost clock speed and therefore single-threaded application performance of these Opteron 4300 and 6300 chips in the works, but AMD has not said yet and will no doubt lay out its plans at Analyst Day this week.

As was the case during the Great Recession, now would be a particularly bad time for AMD to force a socket transition onto its smaller band of server customers, and the new management at AMD must be looking pretty hard at that roadmap, wondering if they can change as little as possible now to buy time to do a lot more radical engineering for the future.

If I were running AMD, I would be looking very hard at that “Bobcat” core that is the alternative to Intel’s Atom and start thinking about servers, and also go back and look at the“Trinity” low-power Fusion chip, which is based on the Bulldozer cores.

When AMD was kicking Intel in the chips in the mid-2000s, Chipzilla relatively quickly (okay, it took years) shifted over to the Core laptop chip architecture for its PCs and servers and not only saved its chip business, but blunted the AMD attack. Intel has copied most of the ideas that made the Opteron better or different and is now using its wafer-baking process technology and its ability to set market prices to force AMD to compete mostly on lower price for roughly equivalent performance and features.

This is not an enviable position to be in for AMD, obviously. But there’s always the ARM option, and AMD could do something radical like buy Applied Micro or Calxeda and turn the x86 chip war into a two-front war for Intel to have to fight. ®

This article originally appeared in The Register. It appears here in its entirety as part of a cross-publishing agreement.

First out of the gate will be Intel with a preview of the “Ivy Bridge” processors for PCs, which are made in its new 22 nanometer Tri-Gate process and which will cram a multicore CPU and a GPU onto the same sliver of silicon. Intel will also be showing off a new dual-core Atom processor implemented in its current and well-established 32 nanometer processes sporting on-chip Wi-Fi networking. This is presumably the “Cedar Trail” family of Atom processors that were originally expected around September, then November, and now sometime next year, according to the rumor mill. Intel will also be showing off a 32-bit x86 chip that has an operating range of between 280 millivolts to 1.2 volts that is implemented in its 32 nanometer processes.

IBM is not saying anything about its future Power7+ or Power8 processors for its Unix and proprietary systems. But Big Blue will be showing off a prototype 3D system-on-chip design that will use through silicon via (TSV) technology that it perfected with Micron Technology for hybrid cube memory. IBM will be demonstrating that the techniques that can be used to stack up DRAM chips and lash them together into a parallel memory cluster (well, that is what HMC memory is, more or less) can be used to link embedded DRAM to processor cores. Such technology will be needed to make more powerful and energy-efficient parallel systems.

Researchers at the Georgia Institute of Technology, Korea Advanced Institute of Science and Technology, and Amkor Technology will be showing off a similar stacked chip called3D-MAPS, which is a massively parallel processor with stacked memory. In this case, the chip in question has 64 cores running at mere 277MHz and 256KB of SRAM memory mated to it. This is a tiny chip in terms of raw chip performance, but it delivers 64GB/sec of memory bandwidth and only consumes 5 watts of juice, and on memory-intensive workloads with a certain degree of parallelism, 3D-MAPS could scream. The next generation 3D-MAPS chip will have two logic tiers with a total of 128 cores and three DRAM tiers instead of one SRAM tier for memory.

The University of Michigan will be stacking up chips, too, with its Centip3De project, which will put 64 ARM Cortex-M3 embedded processors into a cube. The Wolverines have been talking about (PDF) a seven-layer 3D chip that has 128 Cortex-M3 cores and 256MB of stacked DRAM all glued together, so this appears to be a chip off the old block.

Advanced Micro Devices will be showing off a “resonant clock design” for a 64-bit x86-processor towards the end of the day, and clearly there will be a need for some coffee during that one. Fudan University of China will be showing off a 16-core, 320 milliwatt, 800MHz processor it has cooked up with message passing and shared-memory inter-core communications – all cooked up in an ancient and cheap 65 nanometer process. Cavium will be showing off its latest 32-core MIPS-based processors, which sport network accelerators and which are sold under the Octeon II brand. Fujitsu will be there to show off its current K massively parallel supercomputer, powered by the eight-core Sparc64-VIIfx processor and currently the most powerful super in the world.

Hynix Semiconductor and Samsung Electronics will be showing off their respective 2Gbit and 4Gbit DDR4 SDRAM memory chips, which will eventually make their way into PCs and servers. ®

This article originally appeared in The Register. It appears here in its entirety as part of a cross-publishing agreement.